Control chip supporting plurality of buses and control chip...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

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Reexamination Certificate

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07032060

ABSTRACT:
A control chip supporting a plurality of buses and control chip set thereof is provided. A control chip supporting a plurality of buses chooses a type of bus for complying with another control chip based on the bus type thereby, wherein a device and a driving circuit are included. The device generates required controlling timings based on selection pins. The driving circuit enables required transmitting direction of pins based on selection pins per se.

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patent: 6148357 (2000-11-01), Gulick et al.
patent: 6658520 (2003-12-01), Bennett
patent: 6775282 (2004-08-01), Vakkalagadda et al.
patent: 6886066 (2005-04-01), Ishii
Techrepublic, What to expect from the new bus standards, Sep. 24, 2002.
Extremetech, Inside PCI Express, NIck Stam, Sep. 9, 2002.
API Networks, The Hyper Transport Technology (HT) l/O Bus Architecture, white paper, Jun. 15, 2001.

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