Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2005-08-30
2005-08-30
Bragdon, Reginald G. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C365S193000
Reexamination Certificate
active
06938141
ABSTRACT:
A control chip for accelerating the memory access and a method of operating the same is disclosed. The disclosed control chip receives a first address strobe (ADS) signal, a request signal, and an address bus signal from the CPU. A second ADS signal will be promptly issued if the selection phase of the request signal is either a memory read signal or a memory write signal and the address phase of the address bus signal indicates an effective memory address. Thereafter the second ADS signal is converted to a third ADS signal referring to the memory clocks. A memory control signal will be issued if no zero-length signal is suggested in length phase of the request signal and in the byte enable phase of the address bus signal. Computer system performances will be significantly upgraded since the third ADS signal is issued one cycle advanced than conventional approaches.
REFERENCES:
patent: 5784700 (1998-07-01), Chen et al.
Bragdon Reginald G.
Jianq Chyun IP office
VIA Technologies Inc.
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