Control chip and method for accelerating memory access

Details Control chip and method for accelerating memory access Control chip and method for accelerating memory access

2006-07-04

2006-07-04

Vital, Pierre M. (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

C711S150000, C711S210000, C365S189040, C365S189070

Reexamination Certificate

active

07073047

ABSTRACT:
A control chip and operating method for accelerating memory access that can be applied to a memory system whose memory read command actual address is read from a system bus in a number of synchronous transmissions. On receiving a first section read address, the control chip operates to compare the first section read address with an identical bit portion of the write address of the memory-write commands inside a memory-write command queue. If the comparison indicates some difference, permission for executing the memory read command is granted. If the comparison indicates the presence of identical bits, a second section read address is received and compared with an identical bit portion of the write address of the memory-write commands inside a memory-write command queue. If the comparison indicates some difference, permission for executing the memory read command is granted. If the comparison indicates the presence of identical bits, permission for executing the memory read command is granted only after the memory-write command inside the memory-write command queue having an identical write address is executed.

REFERENCES:
patent: 5379379 (1995-01-01), Becker et al.
patent: 5497355 (1996-03-01), Mills et al.
patent: 5954813 (1999-09-01), Mann et al.
patent: 6618724 (2003-09-01), Pollak

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