Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1998-07-22
2001-07-24
Yoo, Do Hyun (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S104000, C711S170000, C365S189011, C326S040000, C326S041000
Reexamination Certificate
active
06266746
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a control apparatus for RAM (Random Access Memory), which controls writing and reading of data with respect to RAM.
2. Prior Art
A known sound signal processing apparatus for processing a sound signal is constructed as shown in
FIG. 1
, by way of example, In this example, the former stage portion outputs a sound signal that has been delayed by a certain time in a RAM (random access memory), to a First-in First-out memory (hereinafter called “FIFO”) in the later stage, and also adds the above sound signal after multiplying it by a certain coefficient, to a newly received sound signal, so that the result of addition is re-stored in the same area or location of the RAM. In this matter, a so-called accumulator function is performed in which effects, such as reverb and echo, are given to the sound signal. In the present specification, the accumulator function means the function to perform a certain operation(s) on data that are read from a given area of the RAM, and re-store the processed data in the same area of the RAM. The later stage portion, on the other hand, performs a FIFO function to output the sound signal to which effects as indicated above have been given in the former stage, at a given rate (sampling frequency) of, for example, 48 kHz. This FIFO function is accomplished by controlling a manner in which data is written into and read from the RAM. In the arrangement in which the FIFO provided in the later stage converts the sound signal at the given rate and outputs the converted signal, DSP, CPU or the like, which operates at an asynchronous, high-speed operating frequency. Such a frequency is not limited to 48 kHz and can be used in the former stage portion.
As in a circuit arrangement shown in
FIG. 2
, the FIFO (pushup storage) is constructed by using a single-port RAM which has a simple structure and is available at a relatively low cost. In
FIG. 2
, a PUSH (write) counter
1
is adapted to update a write address by counting a clock pulse each time a PUSH signal is supplied, and supplies the write address to one of the input terminals of a selecting circuit
3
. A POP (read) counter
2
is adapted to update a read address by counting a clock pulse each time a POP signal is supplied, and supplies the read address to the other input terminal of the selecting circuit
3
. The POP counter
2
also receives the PUSH signal, and is inhibited from operating even if the POP signal is sup-lied thereto while the PUSH signal is effective. The selecting circuit
3
selects one of the write address and the read address according to the PUSH signal. Namely, the selecting circuit
3
supplies the write address to an address input terminal A of the single-port RAM
4
when the PUSH signal is supplied, and supplies the read address to the address input terminal A of the RAM
4
when the PUSH signal is not supplied. The single-port RAM
4
is normally placed in a READ mode, and is turned into a WRITE mode of the PUSH signal is supplied to a write enable terminal WE. The RAM
4
receives data via an input terminal DI, and outputs data through an output terminal DO.
In the above arrangement, if a PUSH signal is supplied, the PUSH (write) counter
1
updates the write address, and supplies the updated address to one of the input terminals of the selecting circuit
3
. At this time, the PUSH signal supplied to the selecting circuit
3
functions as a select signal, and therefore the selecting circuit
3
supplies the write address to the address input terminal A of the single-port RAM
4
. In the single-port RAM
4
, data received through the input terminal DI is written into and stored at the write address as indicated above.
On the other hand, when a POP signal is supplied, the POP (read) counter
2
updates the read address, and supplies the updated address to the other input terminal of the selecting circuit
3
. When a PUSH signal is not supplied, the selecting circuit
3
supplies the read address to the address input terminal A of the single-port RAM
4
. In the single-port RAM
4
, data stored at the read address is generated from the output terminal DO.
The POP counter
2
also receives the PUSH signal, and is inhibited from operating even if the POP signal is supplied thereto while the PUSH signal and the POP signal are simultaneously generated, priority is always given to the PUSH signal, and the POP signal is ignored.
In the known FIFO constructed as described above, when the PUSH signal and POP signal are simultaneously generated, priority must be given to either one of these signals. However, there is a sufficiently high possibility of such simultaneous generation of two types of signals, and, in such a case, the count value of the POP counter
2
is not updated if the POP signal is to be ignored, for example, and the same data is undesirably read from the memory twice.
SUMMARY OF THE INVENTION
It is therefore a first object of the invention to provide a control apparatus for RAM, wherein the RAM is controlled so as to serve as both an accumulator and a FIFO, thus permitting the whole circuit to have a reduced size.
It is a second object of the invention to provide a control apparatus for RAM, wherein priority can be automatically given to one of a write signal and a read signal for writing and reading data with respect to a single-port RAM even when these write and read signals are simultaneously generated, so that both writing and reading operations can be executed.
To attain the first object, according to a first aspect of the invention, there is provided a control apparatus for controlling writing and reading of data with respect to a memory which is randomly accessible, comprising an address producing device which produces an address by a method according to a predetermined rule, in response to a request to access the memory by the method according to the predetermined rule, and a switching device which selects one of an address with which the memory is randomly accessed and the address produced by the address producing device, wherein data is written into and read from the memory, at a location that corresponds to the address that is selected by the switching device and supplied to the memory.
Preferably, the control apparatus further comprises a control device which supplies a switching signal to the switching device to cause the switching device to select one of the address with which the memory is randomly accessed and the address produced by the address producing device, depending upon presence of a request to access the memory by the method according to the predetermined rule and presence of a request to randomly access the memory.
Preferably, the predetermined rule is a first-in first-out method.
In a preferred form of the first aspect, the control apparatus comprises a write address producing device which produces a write address by a method according to a predetermined rule, in response to a write request to write data into the memory by the method according to the predetermined rule, and a write address switching device which selects one of a write address with which data is randomly written into the memory and the write address produced by the write address producing device. A read address producing device which produces a read address by the method according to the predetermined rule, in response to a read request to read data from the memory by the method according to the predetermined rule, and a read address switching device which selects one of a read address with which data is randomly read from the memory and the read address produced by the read address producing device, wherein data is written into the memory at a location that corresponds to the write address selected by the write address switching device and supplied to the memory, and data is read from the memory at a location that corresponds to the read address selected by the read address switching device and supplied to the memory.
Preferably, the control apparatus of the preferred form further comprises
McLean Kimberly
Reed Smith Hazel & Thomas LLP
Yamaha Corporation
Yoo Do Hyun
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