Control apparatus for a memory architecture using dedicated and

Details Control apparatus for a memory architecture using dedicated and Control apparatus for a memory architecture using dedicated and

1996-04-02

1998-06-02

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

364DIG1, G06F 1200

Patent

active

057617279

ABSTRACT:
Disclosed is a memory control device with partitioned memory control for use on a computer system configured based on a shared main memory architecture. The memory control device comprises a main memory controller connected with two sets of access control buses used respectively for partitioned control of the main memory. The main memory is partitioned into a main system dedicated memory segment and a shared resource memory segment respectively for use by the CPU and the peripheral system. A shared data path circuit is used to control data flow on the buses. When the CPU and the peripheral system both want to gain access to the main memory at the same time, the two sets of buses work independently to respectively connect the CPU to the main system dedicated memory segment and the peripheral system to the shared resource memory segment in the main memory for simultaneous, partitioned access to the main memory.

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patent: 5107416 (1992-04-01), Jippo et al.
patent: 5524265 (1996-06-01), Balmer et al.

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