Control and supervisory signal transmission system for...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

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Details

C710S106000, C710S110000

Reexamination Certificate

active

07146450

ABSTRACT:
A parent station output section changes a duty factor between a period in which a control data signal is at a level (high-potential low-level) lower than a power supply voltage Vx but higher than high-level signal in other circuit portions and a subsequent period in which the control data signal is at the power supply voltage Vx level to convert the control data signal into a serial pulse voltage signal and output the voltage signal onto data signal lines D+ and D− in accordance with each data value in the control data signal inputted from a controller in each cycle of a clock.

REFERENCES:
patent: 3870828 (1975-03-01), Saliga
patent: 5223826 (1993-06-01), Amou et al.
patent: 5247292 (1993-09-01), Nakanishi et al.
patent: 5566343 (1996-10-01), Nishiguchi
patent: 5838249 (1998-11-01), Saito et al.
patent: 6310708 (2001-10-01), Ota et al.
patent: 64-72623 (1989-03-01), None
patent: 64-89839 (1989-04-01), None
patent: 3-6997 (1991-01-01), None

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