Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
1998-08-27
2001-07-24
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S147000, C711S151000, C711S173000, C711S170000
Reexamination Certificate
active
06266751
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the shared usage of memory by a plurality of processing agents. In particular, it relates to the efficient and flexible partitioning of shared single-ported memory between a plurality of processing agents.
2. Background of Related Art
With the ever-increasing speeds of today's processors, memory designs have attempted to meet the required speed requirements. Moreover, with the ever-increasing integration of more than one specific task oriented processor for use in a single system, the efficient utilization of fast memory has become a design challenge.
For instance, to achieve fast memory speeds, synchronous dynamic random access memory (SDRAM) technology has been developed for a wide variety of applications to close the gap between the needs of high-speed processors and the access time of non-synchronous memory such as dynamic random access memory (DRAM) or static random access memory (SRAM). Synchronous memory, e.g., SDRAM technology, combines industry advances in fast dynamic random access memory (DRAM) with a high-speed interface.
Functionally, an SDRAM resembles a conventional DRAM, i.e., it is dynamic and must be refreshed. However, the SDRAM architecture has improvements over standard DRAMs. For instance, an SDRAM uses internal pipelining to improve throughput and on-chip interleaving between separate memory banks to eliminate gaps in output data.
The idea of using a SDRAM synchronously (as opposed to using a DRAM asynchronously) emerged in light of increasing data transfer demands of high-end processors. SDRAM circuit designs are based on state machine operation instead of being level/pulse width driven as in conventional asynchronous memory devices. In addition, synchronous memory access techniques improve the margin to system noise because inputs are not level driven. Instead, the inputs are latched by the system clock. Since all timing is based on the same synchronous clock, designers can achieve better specification margins. Moreover, since the SDRAM access is programmable, designers can improve bus utilization because the processor can be synchronized to the SDRAM output.
The core of an SDRAM device is a standard DRAM with the important addition of synchronous control logic. By synchronizing all address, data and control signals with a single clock signal, SDRAM technology enhances performance, simplifies design and provides faster data transfer.
Synchronous memory requires a clock signal from the accessing agent to allow fully synchronous operation with respect to the accessing agent. If more than one agent is given access to a shared synchronous memory, each agent must conventionally supply its own clock signal to the synchronous memory. Unfortunately, the clock signals from separate agents are not conventionally synchronous or in phase with one another. Therefore, as the synchronous memory shifts from the use of one clock signal to another, delays or wait states must be added before the new agent's clock signal can be used to access the synchronous memory.
Some synchronous memory devices have the capability to provide burst input/output (I/O), particularly for the optimization of cache memory fills at the system frequency. Advanced features such as programmable burst mode and burst length improve memory system performance and flexibility in conventional synchronous memories, and eliminate the need to insert wait states, e.g., dormant clock cycles, between individual accesses in the burst.
Conventional SDRAM devices include independent, fixed memory sections that can be accessed individually or in an interleaved fashion. For instance, two independent banks in an SDRAM device allow that device to have two different rows active at the same time. This means that data can be read from or written to one bank while the other bank is being precharged. The setup normally associated with precharging and activating a row can be hidden by interleaving the bank accesses.
Conventionally, each task oriented processing agent had been provided with its own dedicated memory bank system, e.g., as shown in FIG.
6
.
FIG. 6
shows two separate processing agent systems
600
a,
600
b
each having a processing agent
602
,
604
and a dedicated memory bank system
508
a,
508
b,
respectively. Each processing agent
602
,
604
may be a suitable processor, e.g., a microprocessor, a microcontroller, or a digital signal processor (DSP).
Unfortunately, for applications wherein one processing agent requires significant amounts of information from another processing agent, significant delays were caused in transferring the information between the memory bank system of the first processing agent and the memory bank system of the second processing agent to allow the second processing agent to co-process information along with the first processing agent. To reduce the need for transferring information between non-synchronous memory bank systems, shared use of conventional non-synchronous memory using an arbitrator was developed, e.g., as shown in FIG.
7
.
In particular,
FIG. 7
shows a common single-ported memory bank system
508
being accessed by two processing agents
502
,
504
. A multiplexer (MUX)
510
passes the address, data and control busses (ADC) of a selected processing agent
502
,
504
to the common single-ported memory bank system
508
under the control of an arbiter or arbitrator
512
.
As may be appreciated, memory accesses by the separate agents
502
,
504
would clash unless they are arbitrated to allow only one agent to access the common single-ported memory bank system
508
at any one time. Thus, selection logic (i.e., an arbitrator
512
) is conventionally provided to control the multiplexer
510
, which presents the appropriate address, data and control (ADC) signals to the common single-ported memory bank system
508
. Typically, the processing agents
502
,
504
are assigned a hierarchy in the arbitrator
512
for prioritized access to the common single-ported memory bank system
508
, and the arbitrator
512
blocks out accesses by the other agents until finished accessing the common single-ported memory bank system
508
.
Another conventional technique for sharing common single-ported non-asynchronous memory utilizes a memory management address translator
706
as shown in FIG.
8
.
In particular,
FIG. 8
shows two processing agents
702
,
704
accessing a common single-ported memory bank system
508
under the control of a memory management address translator
706
and MUX
708
. The address translation function serves to invisibly index the memory accesses by one of the processing agents
702
,
704
up by a predetermined amount of memory, e.g., 7K as shown in FIG.
8
. Thus, for instance, memory accesses to address
0
by the first processing agent
702
will index through the memory management address translator to a physical address
0
in the common single-ported memory bank system
508
, and memory accesses to address
0
by the second processing agent
704
will index through the memory management address translator to an offset physical address, e.g., 7K in the common single-ported memory bank system
508
.
Unfortunately, address translation is conventionally fixed in shared memory systems and does not provide flexibility in the changing memory needs of the processing agents, particularly as the agents are in operation.
Thus, there is a need for memory systems in general which adjust to the changing needs of a plurality of accessing agents.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, a memory system comprises a plurality of contiguous memory banks collectively having a lowest addressable end and a highest addressable end. A switch is adapted and arranged to switch each of the plurality of contiguous memory banks for access from one of a first processing agent and a second processing agent. A control circuit assigns a first sub-plurality of the contiguous memory banks in increasing order from the lowest addr
Agere Systems Guardin Corp.
Bollman William H.
Chace Christian P.
Kim Matthew
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