Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-07-08
2008-07-08
Nguyen, Than (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S122000
Reexamination Certificate
active
11181117
ABSTRACT:
A memory subsystem includes multiple different caches configured for different types of data transfer operations between one or more processing units and a main memory. The different caches can include a first general cache configured for general random memory accesses, a software controlled cache used for controlling cache operations for different processing devices accessing the same data, and a streaming cache configured for large packet data memory accesses. An arbiter may be used for arbitrating requests by the multiple different caches for accessing the main memory.
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Jalali Caveh
Rowett Kevin Jerome
Sikdar Somsubhra
Sweedler Jonathan
Tran Hoai V.
Mistletoe Technologies, Inc.
Nguyen Than
Stolowitz Ford Cowger LLP
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