Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-04-09
2001-01-16
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S047000
Reexamination Certificate
active
06175247
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to field programmable gate array circuits and systems and, in particular, to context switchable field programmable gate array circuits and systems having publicly and privately shared data.
BACKGROUND OF THE INVENTION
Computer systems have historically evolved such that succeeding generations of computer systems have had progressively greater degrees of flexibility and adaptability. For example, the first computer systems, such as ENIAC, were characterized by fixed hardware and fixed software. That is, a given configuration of hardware and software were capable of performing only a single task and the reconfiguration of either the hardware or the software for a different task was a slow and difficult process. The next major evolutionary generation of computer systems, programmable mainframes, minicomputers and microprocessors, were characterized by fixed hardware and reconfigurable software and were thereby truly programmable, being capable of storing and executing a variety of programs for different tasks.
The current generation of computer systems now includes systems utilizing field programmable gate arrays, that is, hardware comprised of dynamically reconfigurable arrays of basic functional elements, so that these systems are characterized by reconfigurable hardware as well as reconfigurable software. Systems employing field programmable gate arrays are and have been used in applications that demand the performance achieved by application specific circuits and provide the flexibility to adapt from one application to another without the installation of new, application specific hardware for each application. Field programmable gate arrays also allow systems to be upgraded or modified in accordance with rapid design cycles as a hardware reconfiguration requires only the reprogramming of the gate arrays rather than the replacement of a fixed hardware configuration.
Although current field programmable gate arrays have proven adequate and acceptable for many applications, a persistent limitation of current field programmable gate arrays is the time required to reprogram, or reconfigure, current gate arrays from one configuration to another. In the present state of the art, the reconfiguration of a field programmable gate array requires several milliseconds, and as such the reconfiguration time is much longer than the times typically required to complete processes in current computer systems. This limitation thereby prevents computer systems implemented in field programmable gate arrays from achieving run time reconfiguration, that is, the dynamic reconfiguration of system hardware during the execution of a sequence of operations so that the system hardware is optimally configured for each operation.
The prior art has attempted to deal with this limitation by the partial reconfiguration of only selected portions of the field programmable gate array elements and by the use of additional circuits, in excess of those required for system operations at any given time, with system operations switching among sets of circuits while currently unused circuits are reconfigured. In addition to increasing the complexity and cost of a system, these methods have, by there inherent nature, failed to provide a field programmable gate array based system or sub-system that can be reconfigured at a rate that exceeds the necessary persistence of a hardware function. In addition, the systems implemented by these methods have failed to provide a means whereby data may be shared between instantiations of the system hardware configurations, thereby further limiting the speed with which the hardware can be reconfigured because of the need to store and reload data at each change in the hardware configuration.
The present invention provides a solution to these and other problems of the prior art.
SUMMARY OF THE INVENTION
The present invention is directed to a context switching logic cell with data sharing for use in a context switching system.
According to the present invention, a context switching logic cell includes a a programmable logic unit and a context memory. The programmable logic unit is connected from an address/data input for implementing at least one programmable logic function for each context. In the presently preferred embodiment, the programmable logic unit is comprised of a function control memory connected from an address/data input for storing a plurality of sets of configuration bits, each set of configuration bits corresponding to one of a corresponding plurality of contexts and implementing at least one programmable logic function for the corresponding context.
The context memory is connected from the function control memory and includes a plurality of registers, or flip-flops, for storing and providing as an output the results of context dependent logic operations. The context memory registers include a plurality of private registers, at least one public register and an active register. Each private register corresponds to a context and is addressable only within the corresponding context for storing and providing as outputs the results of logic operations in the corresponding contexts. Public registers are addressable within all contexts for storing and providing as outputs the results of logic operations within all contexts, and the active register stores and provides as an output the results of logic operations for the current context.
A context switching logic cell also includes carry logic for receiving a carry bit and generating a carry bit output dependent upon the received carry bit and a current logic operation and may include a data memory that is accessible within all contexts for receiving and storing data and providing a data output to the active register.
Further according to the present invention, the context switching logic cells may be arranged into a context switching logic array for use in a context switching system. A context switching logic array includes a plurality of context switching logic cells arranged in parallel to perform n bit logic operations wherein n is the number of context switching logic cells in the context switching logic array. A context switching logic array further includes a first level bus and dedicated carry bit lines. The first level bus interconnects the address/data inputs and result outputs of the plurality of context switching logic cells into the context switching logic array and provides address/data inputs and result outputs for the context switching logic array. There is a dedicated carry line for and corresponding to each context switching logic cell for communicating carry bits between the context switching logic cells.
Still further according to the present invention, the context switching logic arrays may be arranged into one or more context switching pipelines for use in a context switching system. Each pipeline includes a plurality of context switching logic arrays arranged in series to perform n bit pipelined operations and a second level bus for interconnecting the address/data inputs and result outputs of the context switching logic arrays into the context switching pipeline and to provide address/data inputs and result outputs for the context switching pipeline. Each pipeline will also include, for each context switching logic cell in each context switching array, first and second output interconnections for providing a corresponding output of a corresponding context switching logic cell to inputs of corresponding context switching logic cells in sequentially adjacent context switching logic arrays.
Finally, and according to the present invention, a context switching system may include a plurality of context switching pipelines arranged in parallel, a third level bus for interconnecting the second level buses of the context switching pipelines, dedicated carry lines for and corresponding to each context switching logic array for communicating carry bits between the corresponding context switching logic arrays of the adjacent context switching pipelines.
REFERENCES:
Scalera Stephen M.
Vazquez Jose R.
Clapp Gary D.
Gomes David W.
Lockheed Martin Corporation
Paik Steven S.
Tokar Michael
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