Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Reexamination Certificate
2005-05-31
2005-05-31
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Context preserving (e.g., context swapping, checkpointing,...
C712S215000, C712S216000
Reexamination Certificate
active
06901507
ABSTRACT:
A programmable processing system that executes multiple instruction contexts includes an instruction memory for storing instructions that are executed by the system, fetch logic for determining an address of an instruction, with the fetch logic including scheduling logic that schedules execution of the instruction contexts based on condition signals indicating an availability of a hardware resource, with the condition signals being divided into groups of condition signals, which are sampled in turn by the scheduling logic to provide a plurality of scan sets of sampled conditions.
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Fiske et al., “Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors”, Proceedings of the First Symposium on High Performance Computer Architecture, IEEE, Jan. 22, 1995-Jan. 25, 1995, pp. 210-221.*
Agarwal, et al., “Sparcle; An Evolutionary Processor Design for Large-Scale Multiprocessor”,IEEE Micro, 13(3):48-61 (1993).
Intel Corporation
Treat William M.
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