Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-08-01
2010-06-08
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07735042
ABSTRACT:
A method, system and program product for context aware sub-circuit layout modification are disclosed. The method may include defining at least one context for the sub-circuit for each circuit that uses the sub-circuit; in the case that a plurality of contexts are defined, minimizing a number of contexts for the sub-circuit by combining contexts into at least one stage; placing each stage into a staged layout; and modifying the sub-circuit by modifying the staged layout.
REFERENCES:
patent: 5526279 (1996-06-01), Dick
patent: 5535134 (1996-07-01), Cohn et al.
patent: 6189132 (2001-02-01), Heng et al.
patent: 6904587 (2005-06-01), Tsai et al.
patent: 7484197 (2009-01-01), Allen et al.
patent: 2004/0068712 (2004-04-01), Heng et al.
patent: 2007/0168898 (2007-07-01), Gupta et al.
patent: 2007/0204249 (2007-08-01), Hibbeler
patent: 2007/0240088 (2007-10-01), Tang et al.
patent: 2007/0283301 (2007-12-01), Karandikar et al.
patent: 2008/0313577 (2008-12-01), Tang et al.
Gray Michael S.
Guzowski Matthew T.
Hibbeler Jason D.
McCullen Kevin W.
Walker Robert F.
Hoffman Warnick LLC
International Business Machines - Corporation
Simmons Ryan K.
Whitmore Stacy A
LandOfFree
Context aware sub-circuit layout modification does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Context aware sub-circuit layout modification, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Context aware sub-circuit layout modification will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4233965