Contention resolution in a memory management system

Details Contention resolution in a memory management system Contention resolution in a memory management system

2006-10-10

2006-10-10

Shin, Christopher (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output command process

C710S107000, C711S100000, C711S150000, C711S168000

Reexamination Certificate

active

07120706

ABSTRACT:
A memory management system for resolving contention for access to a plurality of memories. Signals are continuously applied to an access flow regulator indicating the busy/idle state of each memory. The access flow regulator uses the received signals to determine the present busy/idle state of each of the memories. Requests are applied to the access flow regulator for read and write access to the memories. The access flow regulator operates in response to a determination that one of the memories is currently idle for granting a request access to a memory as soon as it switches from a busy to and idle state.

REFERENCES:
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patent: 2002/0029106 (2002-03-01), Shimotani et al.
patent: 2005/0132159 (2005-06-01), Jeddeloh

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