Contention-free signaling scheme for shared control signals

Details Contention-free signaling scheme for shared control signals Contention-free signaling scheme for shared control signals

1999-01-15

2001-08-14

Beausoleil, Robert (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C326S086000

Reexamination Certificate

active

06275883

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the field of high speed data communications, and more particularly, to a transition-based signaling system providing data transfer between multiple controlling elements and multiple controlled elements.
BACKGROUND TO THE INVENTION
For a complex digital system with multiple controlling elements and multiple controlled elements, the number of unique signal paths required for a fully connected graph-type control signal implementation increases dramatically as a function of system complexity. To avoid routing congestion, wasted area for interconnect, and long signal paths, it is desirable to share as many signal paths as possible. For example, in a system with N control units (C
1
, C
2
, C
N
) and M functional units (F
1
, F
2
, . . . F
M
) where each functional unit requires W control signals, in order to implement a system with unique control signal paths linking every control unit to every functional unit, W*N*M separate signal paths are required. If the control units share a single set of signal paths to each functional unit, then only W*M signal paths are required. However, in order to share control signals, it is necessary to have an appropriate signaling scheme and protocol in place for reliable and contention-free communication.
There are a number of signaling schemes for shared signals that have been widely used in the past including tri-state (three-state) and wired-or signaling. One problem with conventional tri-state signaling is the need to rescind an asserted control signal to prevent the controlled functional unit from recognizing the asserted control signal multiple times. Returning to the hypothetical system with N control units described earlier, a control unit C, might assert a group of control signals in cycle i, rescind those signals in cycle i+1, and then tri-state the control signals in cycle i+2. A system operating in this manner would therefore require two overhead clock cycles (cycle i+1 and cycle i+2) each time a control unit finishes asserting a control signal. The overhead can be reduced by causing the control signals to be rescinded in the first half of cycle i+1 and tri-stated in the second half of cycle i+1, but this still requires one overhead clock cycle after assertion of the control signal. Either weak pull-up/pull-down resistors or bus holder cells (weak cross-coupled inverters) can be used to hold the control signals in a negated state in the absence of control activity for an extended period of time, but if bus holder cells are used, then it may be necessary to further include an initialization step to rescind all control signals to a known, inactive state when the system is reset.
If either of the above two signaling schemes is used, and there is more than one control unit, there will be contention between the output drivers of the multiple control units attempting to assert the same control signal in consecutive clock cycles. The attempt by say a second control unit to assert control signals would contend with the rescinding of control signals by say a first control unit. This contention problem can be eliminated through the use of wired-or signaling but at the cost of DC power consumption when control signals are asserted, and potentially long periods time are required to passively rescind asserted control signals when negated. Another approach to eliminating the contention problem is to always rescind control signals in the first half of a clock cycle and design the control units to only assert control signals in the second half. This approach has the disadvantage of providing only a short time window to assert potentially long and heavily loaded signal paths. A need therefore arises for a signaling system which avoids contention between multiple control and functional units without increasing DC power consumption, without limiting assertion times for data transfer, and without imposing significant overhead delays.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a signaling scheme which avoids contention between multiple control and functional units. It is a further object of the invention to implement the above mentioned signaling system without increasing DC power consumption and limiting assertion times for data transfer.
According to the invention, roughly described, a plurality of controlling units and one or more controlled units are connected to a shared bus line, which is also connected to a bus holder cell. Each of the controlling units includes an output circuit that asserts a control signal on the bus line by synchronously asserting a logic level transition on the bus line, and each of the controlled units includes an input circuit that detects assertion of the control signal by detecting that a logic level transition has occurred on the bus line. The synchronous nature of the scheme avoids the possibility of contention because all of the controlling units that intend to assert a logic level transition in a given clock cycle sampled the current logic level at the same time (within the same prior clock cycle). They therefore all agree on the current logic level and will all assert the same opposite logic level when asserting their logic level transition. In addition, detection by the controlled unit input circuits of logic level transitions can be made synchronous as well.
In accordance with an embodiment of the invention, a method for transmitting control data in a transition-based synchronous digital signaling system having at least one controlling unit for receiving commands and outputting control signals and at least one functional unit responsive to the control signals for executing control steps, a method for transmitting control data comprises the steps of: during a first system clock cycle, causing a first logic-level transition on a shared control signal line in response to an asserted command applied to the controlling unit; storing a logic level resulting from the logic-level transition in a control signal state retention cell for the duration of the first clock cycle; during a second clock cycle, causing a second logic-level transition and executing within the functional unit at least one control step carried on the shared control line; sampling the shared control line at the beginning and end of each consecutive system clock cycle for indicating a state transition to the functional unit; whereby the functional unit executes the control step only upon detection of one of the logic-level transitions.
Further in accordance with an embodiment of the invention, a transition-based synchronous digital signaling system comprises at least one controlling unit for receiving a command and outputting a control signal onto a shared control bus; at least one functional unit coupled to the bus responsive to the control signal for executing a control step associated with the asserted command, the functional unit sampling the control bus during each cycle of a system clock; and a state retention cell coupled to the shared control bus for storing state of the control signal; wherein the functional unit executes the control step upon detection of a logic-level transition on the control bus.


REFERENCES:
patent: 4807223 (1989-02-01), Wells
patent: 5153455 (1992-10-01), Walters, Jr.
patent: 5404137 (1995-04-01), Levien
patent: 5619726 (1997-04-01), Seconi et al.
patent: 6104210 (2000-08-01), Stewart

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