Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
2000-08-29
2004-04-06
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S261000, C710S262000, C710S263000, C710S264000, C710S265000, C710S266000, C710S267000, C710S268000, C710S269000, C710S048000, C709S223000
Reexamination Certificate
active
06718413
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to computer systems implementing interrupts, and more particularly to methods for generating interrupts in a host adapter for transferring data to host computer.
2. Description of the Related Art
Modern computer systems often utilize one or more buses to connect to peripheral devices to enhance its resources. For example, the resources of a computer system may be substantially increased by attaching one or more peripheral devices such as disk drives, tape drives, printers, scanners, optical drives, CD-ROM, DVD-ROM, and the like. Generally, the peripheral devices are attached to the computer system by means of a bus (e.g., cable).
One of the most popular buses is the well known small computer systems interface (SCSI) bus, which is defined in conformity with SCSI protocols (e.g., SCSI-1, SCSI-2, SCSI-3, etc.), which are incorporated herein by reference. The SCSI protocols are designed to provide an efficient peer-to-peer I/O interface between a host computer system and its peripheral devices. A SCSI bus may accommodate a plurality of SCSI devices up to :a number equal to the number of data bits in the SCSI bus. For example, the narrow SCSI-2 bus may accommodate up to eight devices, of which one is usually a SCSI host adapter.
The SCSI host adapter is typically provided between a processor and one or more SCSI devices ito facilitate transfer and conversion of data and control signals.
FIG. 1
illustrates a block diagram of an exemplary computer system
100
having a host computer
102
coupled to a plurality of SCSI devices
112
by means of a SCSI bus
114
. The host computer
102
includes a host bus
104
, a processor
106
, a memory
108
, and a SCSI host adapter
110
. The processor
106
is coupled to the bus
104
(e.g., ISA bus, EISA bus, PCI bus, etc.) for processing information such as data and instructions. The memory
108
is also coupled to the bus
104
for storing and providing information for the processor
106
. Although the bus
104
is shown to connect directly between the processor
106
and memory
108
, other configurations with a different processor/memory and bridge to the bus
104
are also possible implementations.
The SCSI host adapter
110
is coupled between the bus
104
and the SCSI bus
114
to interface and communicate information between the host computer
102
and the SCSI devices
112
. Under the current SCSI specifications, the SCSI bus
114
may interconnect up to 7 or 15 target SCSI devices
112
to the host adapter
110
depending on the type of SCSI bus implemented. The target SCSI devices
112
may be devices such as disk drives, tape drives, printers, scanners, optical drives, or any other devices that meet the SCSI specification.
The host adapter
110
provides interface functions and controls communication between the host computer
102
and the SCSI devices
112
using interrupts. Specifically, the host adapter
110
is configured to receive data, address, and control signals from the host computer
102
via the host bus
104
and convert the signals into corresponding SCSI compatible data, address, and control signals. Conversely, the host adapter
104
is also configured to receive SCSI compatible data, address, and control signals from the SCSI devices
112
through the SCSI bus
114
and convert them into corresponding host-bus compatible data, addressing, and control signals. The SCSI host adapter
110
is well known in the art and may be implemented, for example, by using AIC-7890A™ packaged semiconductor device, which is available from Adaptec Inc., of Milpitas, Calif.
As is well known in the art, the communication between the processor
106
and the SCSI devices
112
occurs over various bus phases as defined by SCSI standards.
FIG. 2
shows an exemplary timing diagram
200
of SCSI bus tenancies
228
and
230
involved in transferring data between the host adapter
110
and a selected SCSI device
112
. For an I/O operation such as reading data from the selected SCSI device
112
to the processor
106
, for example, the processor
106
issues a READ command to the host adapter
110
. The host adapter
110
then arbitrates for the SCSI bus
114
during an arbitration (ARB) phase
202
. After gaining arbitration, the host adapter
110
selects the selected SCSI device
112
as the target in a selection (SEL) phase
204
. At this time, the target receives the SCSI ID of the host adapter
110
so that it may reselect the host adapter
110
in a reselect phase.
Once the target has been selected, the host adapter
110
provides, during a message tag (MSG TAG) phase
206
, a message to the target identifying the specific command transferred during this selection for future reference by the target. The host adapter
10
then issues the READ command to the selected target during a COMMAND (CMD) phase
208
. Then, the communication between the host adapter
110
and the target is typically terminated in a message disconnect (MSG DISC) phase
210
to allow other devices access to the bus. At this time, the SCSI bus enters into a bus free phase
212
indicating the end of the command phase and the availability of the SCSI bus for other devices. The phases
202
to
210
are commonly known as command tenancy
228
.
Following the bus free phase
212
, the selected SCSI device re-establishes connection with the host adapter
110
to continue the interrupted transaction for transferring data during data tenancy
230
. Specifically, the selected SCSI device arbitrates for the bus in an arbitration phase
214
and then reselects the host adapter, which functions as a target, during a reselection (RE-SEL) phase
216
. Then, the target sends a reconnect message (MSG RECON)
218
followed by a tag message (MSG TAG)
220
in a message phase. This informs the host adapter
110
which command the following data and status phases are for. Then, data is transferred from the selected SCSI device to the host adapter
110
for use by the host processor during a data phase
222
. During a following status (STATUS) phase
224
, the SCSI device provides well known status information to the host adapter
110
to indicate success or failure of the command. When the status phase
224
ends, the SCSI device passes a command complete (CMD COMP) message in a command complete phase
226
to indicate that the command has been completed. Following the command complete phase
226
, the SCSI bus again enters into another bus free phase. The phases
214
to
226
are often called data tenancy
230
.
In conventional computer systems, a host adapter typically generates an interrupt signal at the end of the I/O command complete phase
226
and sends the signal to the processor. This signal informs the processor that the previously requested data have been transferred, for example, via a DMA transaction. The interrupt signal interrupts the processor from its current task and causes the processor to make use of the transferred data.
Given that processors in modern computer systems are highly pipelined, interrupt reception can cause a substantial loss of useful computation time, thereby resulting in reduced system throughput. Hence, it is desirable to reduce the number of interrupts to a minimum required for adequate responsiveness. For SCSI host adapters, this has involved reducing the number of interrupts to a fraction of the number of I/O command completions.
A widely used technique called “interrupt batching” reduces interrupts by batching (i.e., accumulating) a number of I/O command completions together to generate a single interrupt. For example, this approach waits a specified period of time after completion of a task (i.e., command completion) to determine if any more tasks are completed. It may also wait for a specified number of command completions. In either case, this technique monitors the command completions for the specified duration or number. An interrupt is then asserted either, after the expiration of the specified period or upon reaching the specified number of comp
Busing Darren R.
Luu Trung S.
Wilson Andrew W.
Young B. Arlen
Adaptec, Inc.
King Justin
Martine & Penilla LLP
Ray Gopal C.
LandOfFree
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