Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
1999-12-17
2001-07-24
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S095000, C326S098000, C326S113000
Reexamination Certificate
active
06265897
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to complementary metal oxide semiconductor (CMOS) integrated circuits of a type referred to as contention based logic gates and more particularly to such a logic gate that is driven by a pulsed clock source and has an output that is latched.
BACKGROUND ART
Classic CMOS logic circuits include N-channel pull-down circuitry and P-channel pull-up circuitry connected between ground and positive DC power supply terminals or rails of an integrated circuit chip. An output terminal between the N-channel and P-channel circuitry supplies circuitry downstream of the logic gate with a bi-level output signal, typically a voltage substantially at one of the rail voltages. The pull-up circuitry and pull-down circuitry are driven in parallel by binary input signals supplied to the logic gate. Usually, the pull-up circuitry includes multiple P-channel field effect transistors (FETs), while the pull-down circuitry includes N-channel FETs. In response to the logic function of the logic circuit being satisfied, the pull-up circuitry is activated to supply the voltage at the positive power supply terminal to the output terminal. If the logic function is not satisfied, the pull-down circuitry is activated to supply the low, typically ground power supply voltage to the output terminal. To provide these connections, the P-channel pull-up and N-channel pull-down circuitry include numerous elements. Such an arrangement requires significant space on the integrated circuit chip and complex components necessary to form the pull-up and pull-down circuits.
Contention based logic gates were developed to overcome the problems associated with the classic pull-up and pull-down circuit approach. Pseudo-NMOS logic gates are one type of contention based logic gates. A typical pseudo-NMOS logic gate includes a single P-channel FET connected between the positive rail and an output terminal and pull-down circuitry connected between the output terminal and ground rail. The P-channel field effect transistor connected between the positive rail and the output terminal has a gate electrode that is usually connected to ground, so that the P-channel FET is always biased on to a certain extent. If the logic function (which determines the configuration of the N-channel pull-down circuitry) is satisfied, the pull-down circuitry has a high impedance between the output terminal and the grounded rail so that the voltage at the positive DC power supply rail is coupled through the P-channel FET to the output terminal, causing the output terminal to be at a high voltage. If the logic function is not satisfied, the pull-down circuitry provides a low impedance between the output terminal and the grounded rail. The low impedance of the pull-down circuitry is considerably lower than the turn on impedance of the P-channel FET so that the output terminal is at a voltage substantially less than one-half of the voltage between the power supply rails, i.e., the voltage at the output terminal is lower than a threshold associated with circuits driven by the pseudo-NMOS logic gate.
A problem with the traditional pseudo-NMOS logic gate is that the P-channel FET is always biased on and is drawing current from the positive power supply rail. The power dissipation has deleterious effects on the device, particularly with regard to heat.
Clocked pseudo-NMOS logic gates were developed to limit the current flowing through the P-channel transistor connected between the gate output terminal and positive power supply rail during one phase, i.e., portion, of each clock cycle. In a typical clocked pseudo-NMOS logic gate, each clock cycle is divided into two approximately equal duration phases or portions (i.e., each cycle includes two approximately equal half cycles) so that during a first clock cycle phase, the clock wave is at a positive voltage level, i.e., binary one level, and during a second phase the clock wave has a low voltage (i.e., approximately ground) or binary zero level. Such a clock wave is applied to the P-channel FET so current flows through the P-channel FET only during approximately fifty percent of each clock wave cycle. Hence, the percentage of time power is dissipated in the P-channel FET is reduced by approximately fifty percent.
However, for many applications the fifty percent duty cycle of the P-channel FET of the clocked pseudo-NMOS logic gate is excessively high. Simply reducing the on time of the P-channel FET to a lower than fifty percent duty cycle does not, in many instances, permit downstream circuitry driven by the clocked pseudo-NMOS logic gate to adequately detect the result of the output signal of the logic gate, i.e., to detect whether the logic function of the gate has been satisfied by the input signals thereof. This is particularly the case for high frequency circuits having clock frequencies in the one GigaHertz range.
It is, accordingly, an object of the present invention to provide a new and improved contention based logic gate.
Another object of the present invention is to provide a new and improved contention based logic gate having a duty cycle substantially less than fifty percent and wherein circuitry driven by the gate can be responsive to the gate output, even though the gate is driven at very high frequencies, for example, in the one GigaHertz range or higher.
Another object of the invention is to provide a new and improved pseudo-NMOS gate having low power dissipation as a result of low duty cycle operation, wherein the gate can be responsive to a large number of input signals.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention, a logic circuit arrangement on an integrated circuit chip comprises a timing arrangement responsive to a clock pulse source for deriving a PSEUDO clock wave having an enable value interval that is substantially less than one-half a cycle of the clock wave. The PSEUDO clock wave causes a contention based logic gate to derive a logic level determined by binary inputs supplied to the logic gate and a predetermined logic function of the logic gate during the interval while the PSEUDO clock wave has the enable value. A latching circuit responds to the output of the contention based logic gate only during the interval when the PSEUDO clock wave, as coupled to the latching circuit, has the enable value. The latching circuit is activated only during at least some of the enable portion of the clock wave.
Another aspect of the invention concerns a method of operating a contention based logic gate on an integrated circuit chip having CMOS circuitry and responsive to a clock source. The method includes enabling: (1) the contention based logic gate to be responsive to logic input signals applied to it for a time interval that is substantially less than one-half a cycle of the clock source, and (2) a latching circuit to be responsive to an output signal derived by the logic gate only while the logic gate is enabled.
Enabling steps (1) and (2) are preferably performed by shaping a clock wave derived by the clock source into at least one PSEUDO clock wave having an enable interval substantially equal to the enable interval of the logic gate and latching circuit, and by applying the PSEUDO clock wave to the logic gate.
In the preferred embodiment, the clock wave is shaped into first and second PSEUDO clock waves. The applying step includes applying the first PSEUDO clock wave to the logic gate and applying the second PSEUDO clock wave to the latching circuitry. The first PSEUDO clock wave has an enable interval exceeding the enable interval of the second PSEUDO clock wave and the enable interval of the second PSEUDO clock wave occurs simultaneously with a portion of the enable duration of the first PSEUDO clock wave.
A further aspect of the invention relates to an integrated circuit chip having a logic circuit arrangement including: (1) a gate having an output terminal, (2) a first switch connected between the output terminal and a first DC power supply terminal, and (3) logic circuitry responsive to multiple binary input
Kever Wayne Dervon
Naffziger Samuel D
Poirier Christopher Allan
Hewlett--Packard Company
Paik Steven S.
Tokar Michael
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