Content based yield prediction of VLSI designs

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07661081

ABSTRACT:
An integrated circuit system and program product for predicting yield of a VLSI design. An integrated circuit system is provided including a system for identifying and grouping sub-circuits contained within an integrated circuit design by circuit type; a critical area calculation system for determining critical area values for different regions, wherein each different region is associated with a circuit type; a tallying system for calculating a plurality of tallies of critical area values based on circuit type; and a plurality of modeling subsystems for separately modeling each of the plurality of tallies based on circuit type.

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J. Khare et al., “Accurate Estimation of Defect-Related Yield Loss in Reconfigurable VLSI Circuits,” IEEE Journal of Solid State Circuits, vol. 28, No. 2, Feb. 1993, pp. 146-156.
C.H. Stapper, “Modeling of Integrated Circuit Defect Sensitivities,” IBM J. Res. Develop., vol. 27, No. 6, Nov. 1983, pp. 549-557.
C.H. Stapper et. al., “Yield Model for ASIC and Processor Chips,” 1993 IEEE Int'l Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 136-143.

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