Content addressable memory with an internally-timed write...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition

Reexamination Certificate

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Details

C365S049130, C365S050000, C711S118000, C711S150000, C711S155000, C711S167000, C711S168000, C711S169000

Reexamination Certificate

active

06230237

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to digital memories, and more particularly, to a content addressable memory with an internally-timed write operation.
BACKGROUND ART
A Content Addressable Memory (CAM) is a memory unit that is used to compare an input data word to a number of stored data words. For each stored data word that matches the input data word, a match signal is asserted. If none of the stored data words matches the input data word, a read miss occurs and no match signal is asserted.
One example of a CAM application is a translation buffer that is used in a virtual memory system, where the input data word is a virtual address. If a match is found for the virtual address, the resulting match signal is used to select a corresponding physical address from an associated memory unit. If a read miss occurs, the virtual address is written to a CAM entry determined by a replacement rule, and the corresponding physical address is written to the associated memory unit. CAMs are also widely used in cache memory systems including, for example, fully associative caches.
As in the virtual memory system described above, the input data word is typically written to the CAM subsequent to a read miss. However, as conventionally implemented, the writing step is not automatic. External control logic is required to sense the read miss and generate a CAM write cycle in which the input data word is written to the CAM. Normally, this step requires one or more clock cycles after the read miss occurs. Thus, conventional approaches waste one or more clock cycles in updating the CAM with the input data word, which can have a cumulative effect over time.
Accordingly, what is needed is a CAM in which the input data word is automatically written responsive to a read miss without externally coupled control logic. What is also needed is a CAM in which the input data word is automatically written to one or more CAM entries in the same clock cycle as the comparison operation, using an internally-timed write operation.
SUMMARY OF THE INVENTION
The present invention is directed to a content addressable memory with an internally-timed write operation. In accordance with the present invention, a data input is provided for receiving an input word. Coupled to the data input are a plurality of storage registers comprising stored words. Each storage register includes a comparison circuit for comparing the stored word with the input word and producing therefrom a match output indicating a match when the stored word matches the input word, and indicating a miss when the stored word does not match the input word. Coupled to the storage registers is a miss detector for generating a miss signal responsive to each of the match outputs of the storage registers indicating a miss. Coupled to the miss detector is a write cycle circuit for writing the input word to at least one of the storage registers responsive to receiving the miss signal.
The present invention is also directed to a method for automatically updating a content addressable memory responsive to a read miss, including the steps of receiving an input word; comparing the input word with a plurality of stored words; and responsive to the input word matching none of the stored words, writing the input word to at least one storage register of the content addressable memory.


REFERENCES:
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patent: 5329629 (1994-07-01), Horst et al.
patent: 5568415 (1996-10-01), McLellan et al.
patent: 5784709 (1998-07-01), McLellan et al.
patent: 5890201 (1999-03-01), McLellan et al.
patent: 5893137 (1999-04-01), Parks et al.
patent: 6041405 (2000-03-01), Green

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