Content addressable memory system with self-timed signals and ca

Details Content addressable memory system with self-timed signals and ca Content addressable memory system with self-timed signals and ca

1997-09-04

2000-09-19

Gossage, Glenn

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

365 49, G06F 1300, G11C 1500

Patent

active

061227072

ABSTRACT:
A system includes a plurality of content addressable memory (CAM) arrays and a plurality of logic circuits. The logic circuits are connected to a commonly shared bus. Each of the logic circuits is associated with the respective CAM array. Each of the CAM arrays provides search results (hit, match address and multiple match) in a search operation in response to a clock signal. The hit signals provided from the CAM arrays to the respective logic circuits. Each logic circuit provides an OR logic output signal from a hit signal input from an upstream logic circuit and the hit signal provided by the CAM array associated with that logic circuit, in response to a self-timed signal which is delayed in time from the clock signal. The OR logic output signal provided by the logic circuit is provided to a downstream logic circuit. Thus, the furthest downstream logic circuit provides a hit result of the system in a search operation.

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"Self-Timed Hit Circuit for a Content Addressable Memory", IBM Technical Disclosure Bulletin, vol. 38, No. 2, Feb. 1, 1995, pp. 65/66.

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