Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1997-08-28
2001-05-08
Gossage, Glenn (Department: 2759)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S005000, C365S049130, C365S230030, C365S210130
Reexamination Certificate
active
06230236
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a content addressable memory (CAM) system in which a plurality of CAM chips are cascade-connected.
BACKGROUND INFORMATION
In known CAMs, data is selected based on contents, rather than physical location. This function is useful for many applications, especially when performing a look-up for the purposes of mapping a long identification word data to a shorter word data. This operation is required in many telecommunication (telecom) functions, including Asynchronous Transfer Mode (ATM) address translation.
Often, system storage requirements exceed the number of entries stored on a single CAM chip. Multiple chips are then required, and it is necessary that a means be developed to cascade these multiple chips such that they may be searched as a single entity. An appropriate “user-friendly” cascading capability enables the same chip to be used in a range of systems with different capacity requirements, and allows for easy expandability and scalability, as well.
U. S. Pat. No. 5,568,416 granted to K. Kawana et al on Oct. 22, 1996 discloses an associative memory in which multiple CAM chips are cascaded by propagating a result address and status through all chips in the cascade. Each chip contains a status register for itself, and another for all upstream chips. It also discloses means of identifying the last device in the cascade, and separate storage areas for common and unique data entries.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved content addressable memory system.
According to one aspect of the present invention, there is provided a system comprising a common bus and a plurality of content addressable memory (CAM) chips which are cascaded and connected to the common bus, each of the CAM chips comprising: encoding means; an array of core cells, of w words×b bits, associated with the encoding means, each core cell comprising data storage means; timing circuitry for generating a self-timed signal in response to a clock signal, the self-timed signal being used for a search operation on that CAM chip, each CAM chip being able to provide, through its respective encoding means, hit and match address signals resulting from a search operation in response to the self-timed signal; and logic means for transferring the match address signal to the common bus in response to the self-timed signal, the hit signal resulting from the search operation and a propagation-in hit signal provided from an upstream CAM chip.
For example, the logic means includes AND gate means and transfer gate means. The AND gate means logically combines the self-timed signal, the hit signal and the propagation-in hit signal to provide an enable signal. The transfer gate means transfers the match address signal to the common bus in response to the enable signal provided by the AND gate means. In the system, the transfer of the match address signal to the common bus is controlled by a logically combined signal of the self-timed signal, the hit signal and the propagation-in hit signal, so as to prevent more than one CAM chip from providing the match address signal to the common bus simultaneously.
According to another aspect of the present invention, there is provided a system comprising a common bus and a plurality of content addressable memory (CAM) chips which are cascaded and connected to the common bus, each of the CAM chips comprising: encoding means; an array of core cells, of w words×b bits, associated with the encoding means, each core cell comprising data storage means; timing circuitry for generating a self-timed signal in response to a clock signal, the self-timed signal being used for a search operation on that CAM chip, each CAM chip being able to provide, through its respective encoding means, hit and match address signals resulting from a search operation in response to the self-timed signal; and logic means for providing a propagation-out hit signal to a downstream CAM chip in response to the self-timed signal, the hit signal resulting from the search operation and a propagation-in hit signal provided from an upstream CAM chip.
For example, the logic means includes OR gate means for logically combining the self-timed signal, the hit signal and the propagation-in hit signal to provide the propagation-out hit signal. In the system, the self-timed signal, the hit signal of one CAM chip and the propagation-in hit signal from an upstream CAM chip are ORed to provide a propagation-out hit signal, so that a hit signal is propagated from an upstream CAM chip to a downstream CAM chip.
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Gibson Garnet Frederick Randall
Schultz Kenneth James
Shafai Farhad
de Wilton Angela C.
Gossage Glenn
Nortel Networks Corporation
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