Content addressable memory device capable of comparing data...

Details Content addressable memory device capable of comparing data... Content addressable memory device capable of comparing data...

2002-06-19

2004-07-06

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S049130, C365S198000, C365S190000

Reexamination Certificate

active

06760249

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
This invention relates to NMOS semiconductor memories, and more particularly to content-addressable memory (CAM) cells.
BACKGROUND OF THE INVENTION
Most memory devices store and retrieve data by addressing specific memory locations. As a result, this path often becomes the limiting factor for systems that rely on fast memory accesses. The time required finding an item stored in memory can be reduced considerably if the item can be identified for access by its content rather than by its address. A memory that is accessed in this way is called content-addressable memory or CAM. CAM provides a performance advantage over other memory search algorithms, such as binary or tree-based searches, by comparing the desired information against the entire list of pre-stored entries simultaneously, often resulting in an order-of-magnitude reduction in the search time.
CAM is ideally suited for several functions, including Ethernet address lookup, data compression, pattern-recognition, cache tags, high-bandwidth address filtering, and fast lookup of routing, user privilege, security or encryption information on a packet-by-packet basis for high-performance data switches, firewalls, bridges and routers.
Since CAM is an outgrowth of Random Access Memory (RAM) technology, in order to understand CAM, it helps to contrast it with RAM. A RAM is an integrated circuit that stores data temporarily. Data is stored in a RAM at a particular location, called an address. In a RAM, the user supplies the address, and gets back the data. The number of address line limits the depth of a memory using RAM, but the width of the memory can be extended as far as desired. With CAM, the user supplies the data and gets back the address. The CAM searches through the memory in one clock cycle and returns the address where the data is found. The CAM can be preloaded at device startup and also be rewritten during device operation. Because the CAM does not need address lines to find data, the depth of a memory system using CAM can be extended as far as desired, but the width is limited by the physical size of the memory.
CAM can be used to accelerate any application requiring fast searches of data-base, lists, or patterns, such as in image or voice recognition, or computer and communication designs. For this reason, CAM is used in applications where search time is very critical and must be very short. For example, the search key could be the IP address of a network user, and the associated information could be user's access privileges and his location on the network. If the search key presented to the CAM is present in the CAM's table, the CAM indicates a ‘match’ and returns the associated information, which is the user's privilege. A CAM can thus operate as a data-parallel or Single Instruction/Multiple Data (SIMD) processor.
CAM can be used to accelerate any applications ranging from local-area networks, database management, file-storage management, pattern recognition, artificial intelligence, fully associative and processor-specific cache memories, and disk cache memories. Although CAM has many applications, it is particularly well suited to perform any kind of search operations.
Each CAM cell is essentially a RAM cell with a match function. Match functions can be implemented by adding an exclusive-OR (XOR) or inverse XOR gate to each RAM cell. The XOR output is applied to a match line that connects many CAM cells together in a row or column. The match signal can then be output from the memory.
CAM cells were originally constructed from static RAM (SRAM) cells by adding transistors to perform the XOR function. More recently, CAM cells have also been constructed from dynamic RAM (DRAM) cells. DRAM cells have an area and cost advantage over SRAM cells since a small capacitor stores charge rather than a bi-stable or cross-coupled pair of transistors.
FIG. 1
shows a prior-art dynamic CAM cell using six transistors. U.S. Pat. No. 5,428,564 by Winters shows a six-transistor (6T) CAM cell based on earlier dynamic CAM cells of just 4 or 5 transistors. While the earlier 4T and 5T CAM cells were small in area, these cells were particularly noise sensitive and slow, having relatively low voltage ratios. Winter's CAM cell uses only n-channel (NMOS) transistors, and has a small area. However, bit-line capacitance is high, the high bit-line capacitance slows read and write operations.
FIG. 2
is a conventional dynamic CAM cell using CMOS transistors. See U.S. Pat. No. 4,791,606 by Threewitt et al. A single bit of data is stored on capacitor when pass transistor is activated by word line WL. Only one bit line BL is used. While such a CMOS CAM cell is useful, integrating p-channel transistors into each cell is expensive. The spacing from a p-channel transistor to an n-channel transistor is large, since separate P and N wells must be made. The spacing between two n-channel transistors is much smaller. Thus the size of the cell is larger when p-channel transistors are included with the r-channel transistors. Also, a single bit line makes reading and writing slow since an absolute voltage rather than a voltage difference is sensed or driven.
What is desired is a CAM cell using only n-channel transistors or p-channel transistors. It is desired to use dynamic storage rather than static storage to reduce the size of the CAM cell.
SUMMARY OF THE INVENTION
The invention provides NAND or NOR content-addressable memory (CAM) cells, which selectively use single port, tow ports, or three ports for operations depending on design requirements. These NAND or NOR CAM cells are designed by only n-channel transistors or p-channel transistors. In such designs, one-port bit line with one-port word line, or one-port bit line with two-port word lines, or two-port bit lines with two-port word lines are provided for meeting different purposes.
One arrangement with two-port word lines can be one port word line for refresh and other port word line for SRAM write operation. One of the other arrangements with two-port word lines can be one port word line for read operation and other port word line for write operation, while a wave-pipeline technique is used for refresh cycle (which means hidden refresh). One of the other arrangements with two-port word lines can be one port word line for read operation and other port word line for write operation, while idle a refresh cycle for such dynamic CAM cell.
One arrangement with two-port bit lines can be a match operation and a read/write operation can be performed in the same cycle, while a wave-pipeline technique is used for refresh cycle (which means a hidden refresh method). One of the other arrangements with two-port bit lines is a match operation and a read/write operation can be performed in the same cycle, while idle one cycle for refresh. One of the other arrangements with two-port bit lines is and two-port word line can be one word-line port for refresh and the other word-line port for a SRAM write operation, while the match operation can be performed in the same cycle. One of the other arrangements with two-port bit lines is and two-port word line can be one word-line port for read operation and the other word-line port for write operation, while a wave-pipeline technique for hidden refresh is used for a refresh cycle (which means hidden refresh) and the match operation can be performed in the same cycle. One of the other arrangements with two-port bit lines is and two-port word line can be one word-line port for read operation and the other word-line port for write operation, while the match operation is performed in the same cycle and idle a refresh cycle for refresh operation (for dynamic CAM cells). Such 3-port dynamic differential CAM cells can be implemented by any CMOS technologies, such as FRAM, DRAM, logic technology, etc. These CAM cells can be combined and modified in accordance with different purposes.
As embodied and broadly described herein, the invention provides a memory cell, comprising a first bit line, for transmitting

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