Content addressable memory device

Details Content addressable memory device Content addressable memory device

2002-05-22

2004-04-06

Tran, M. (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S221000

Reexamination Certificate

active

06717831

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to Korean Patent Application No. 2001-62847, filed on Oct. 12, 2001.
BACKGROUND
1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly to a content addressable memory device having improved integration density and speed.
2. Description of Related Art
A content addressable memory (CAM) is a memory device comprising a plurality of CAM cells for storing data. A CAM memory is commonly used as a tag memory for storing addresses of a cache memory when high speed operation is needed. A CAM cell comprises a static random access memory (SRAM) and a comparing circuit, and is connected to a match line. The comparing circuit of the CAM cell compares the data stored in the SRAM with the data inputted through bit lines, and outputs a match signal to the match line when the compared data is similar.
More specifically, a typical CAM array comprises CAM cells arranged in a matrix format comprising rows and columns. The CAM cells on one row are connected to a match line, and the CAM cells on one column are connected to bit lines. Each CAM cell in the CAM cell array compares the data stored therein with the data inputted through the bit lines corresponding to the CAM cell. If the compared data is different, the CAM cell discharges the match line. The discharged voltage level of the match line indicates that a mismatch exists in a column of the CAM array. The mismatch in the column of the CAM array may be indicated by any one CAM cell connected to the column by discharging a corresponding match line.
FIG. 1
illustrates an exemplary CAM cell
10
disclosed in Korean Patent. No. 2000-250807 entitled “A field configurable RAM and programmable logic array memory using a CAM cell structure and a CAM cell” issued to Lee Gui-ro et al. The CAM cell
10
comprises an SRAM having inverters
11
and
12
and N channel metallic oxide semiconductor (NMOS) transistors
13
and
14
, and a comparing circuit having NMOS transistors
15
,
16
and
17
.
The NMOS transistors
15
and
16
have current paths formed in series between bit lines BL, /BL, and gates connected to nodes N
1
and N
2
, respectively. The NMOS transistor
17
has a gate connected to connection node N
3
of the NMOS transistors
15
and
16
and to a current path formed between a match line ML and a ground voltage.
If the data input to bit lines BL, /BL is identical with the data stored in the SRAM, a pre-charged state of the match line ML is maintained. However, if the data input to bit lines BL, /BL is different from the data stored in the SRAM cell, the level of node N
3
becomes high by the NMOS transistor
15
or
16
. As a result, the NMOS transistor
17
is turned on to discharge the pre-charged match line ML.
The CAM cell
10
has a superior integration density because only three transistors construct the comparing circuit. One disadvantage of the CAM cell
10
is that the NMOS transistor
17
operates at slow speed because the power source voltage level of the data inputted through the bit line BL or /BL to the NMOS transistor
17
is lowered by a threshold voltage Vth of the NMOS transistor
15
or the NMOS transistor
16
.
FIG. 2
illustrates another exemplary CAM cell
30
disclosed in U.S. Pat. No. 5,396,449 entitled “Fast content addressable memory with reduced power consumption” issued in 1995 to Francois et al. The CAM cell
30
comprises a SRAM cell having inverters
31
,
32
and NMOS transistors
33
,
34
, and a comparing circuit having NMOS transistors
35
,
36
,
37
and
38
.
The NMOS transistors
35
,
36
have current paths formed sequentially in series between a match line and a ground voltage, and gates connected to a bit line BL and a node N
5
, respectively. The NMOS transistors
37
,
38
have current paths formed sequentially in series between a match line and a ground voltage, and gates connected to a bit line /BL and node N
4
, respectively. The bit lines BL, /BL transmit complementary data to the CAM cell
30
, respectively.
If the data input to bit lines BL, /BL is identical with the data stored in the SRAM cell, a pre-charged state of the match line ML is maintained. On the contrary, if the data is different from each other, the match line ML is discharged to a ground voltage by the transistors
35
and
36
or
37
and
38
, which are serially connected to each other.
The CAM cell
30
has a superior integration density because all of the transistors constructing the comparing circuit are NMOS transistors, and the CAM cell
30
operates at a low power because only gates of transistors
35
,
36
,
37
, and
38
are operated. But, the CAM cell
30
of
FIG. 2
has a greater size than the CAM cell
10
of
FIG. 1
, because the CAM cell
30
has four transistors
35
,
36
,
37
and
38
to form two current paths for discharging the match line ML while the CAM cell
10
of
FIG. 1
has only one transistor
17
to discharge the match line ML. Thus, the CAM cell
30
has increased circuit area.
FIG. 3
illustrates another exemplary CAM cell
50
disclosed in the U.S. Pat. No. 5,490,102 entitled “Low capacitance content-addressable memory cell” issued in 1996 to Farah. The CAM cell
50
comprises a SRAM having inverters
51
,
52
and NMOS transistors
53
,
54
, and a comparing circuit having NMOS transistors
55
,
57
and PMOS transistors
56
,
58
. The transistors of the comparing circuit are arranged into two pass gates, for example, transistors
55
and
56
for receiving the data input through a bit line BL, and transistors
57
and
58
for receiving the data input through a bit line /BL.
If the data input through the bit lines BL, /BL are identical with the data stored in the SRAM cell, the level of node N
10
becomes low, so that an NMOS transistor
59
is turned off and a match line ML maintains a pre-charged level. However, if the data inputted through the bit lines BL, /BL is different from the data stored in the SRAM cell, the level of node N
10
becomes high to discharge the match line ML.
The CAM cell
50
operates at faster speed than the CAM cell
30
of
FIG. 2
by using NMOS and PMOS transistors in a comparing circuit, but the CAM cell
50
has a low integration density since the PMOS transistor occupies a greater area. Further, since the transistors
55
,
56
,
57
and
58
are operated in response to the data stored in the SRAM, the CAM cell
50
consumes high power.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a content addressable memory that provides high integration density, with high operation speed and low power consumption.
According to one aspect of the present invention, a content addressable memory device comprises a memory cell connected between first and second nodes, first and second data lines for transmitting first and second data signals to the first and second nodes, respectively, and first and second switching devices serially connected between a match line and a reference voltage, wherein the first switching device is controlled by the first data signal and a voltage of the first node and the second switching device is controlled by the second data signal and a voltage of the second node. Preferably, one of the first and second switching devices is turned off when a voltage level of the first data signal is similar to a voltage level of the first data signal and a voltage level of the second node is similar to a voltage level of the second data signal. Both the first and second switching devices are turned on when the voltage level of the first data signal is different from the voltage level of the first data signal and the voltage level of the second node is different from the voltage level of the second data signal.
According to another aspect of the present invention, a content addressable memory device comprises a memory cell for latching in first and second data signals on first and second nodes from first and second data lines, respectively, a first switching device comprising a first terminal connected t

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