Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
1999-12-30
2001-02-27
Mai, Son (Department: 2818)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S189070, C365S203000
Reexamination Certificate
active
06195278
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to Content Addressable Memory (CAM) and, in particular, to cells and words within CAM arrays.
BACKGROUND OF THE INVENTION
CAMs are memories in which data is elected based on its contents, rather than its physical location. This function is useful for many applications, especially when performing a look-up for the purposes of mapping from a long identification word to a shorter word. This operation is required in many telecom functions, including Asynchronous Transfer Mode (ATM) address translation.
The design of a standard CAM comprises an array of individual CAM cells configured into rows and columns. Typically, each individual CAM cell can store a single bit of data during a write operation and compare that stored bit with a reference bit during a comparison operation, this comparison operation determining if the stored bit and the reference bit match. In one common implementation, each row represents a different one of w words of b bits, the number of rows and columns equalling w and b respectively. Within a comparison operation, the bits of data stored within the CAM cells of a single word are each compared to a different reference bit, the reference bits together combining to generate a reference data word. If each and every one of the reference bits within the reference data word matches its corresponding stored bit within the stored word, a match is deemed to be achieved. Otherwise, the match has failed.
For the common implementation described above, the total number of CAM cells within an array equals the number of words multiplied by the number of bits per word (wxb). Hence, despite the power and speed of each individual CAM cell not significantly effecting the overall operation of the CAM, the large number of CAM cells required in a standard CAM makes the design of the CAM cell particularly critical to the performance parameters of a standard CAM. These performance parameters include the power consumption, reliability and overall speed of the CAM.
There are numerous well-known embodiments for CAM cells, each of these embodiments having different advantages and disadvantages. Some common CAM cell designs, as depicted in
FIG. 1A
for instance, are implemented within a NOR configuration such that the CAM cells are coupled together by a match line
20
which is precharged to a logical high. In these designs, a mismatch between the stored bit and the reference bit causes one of two n-channel pass transistors
22
to forward a logical high to the gate of an n-channel pull-down transistor
24
coupled to the match line
20
. This logical high turns on the n-channel pull-down transistor
24
which results in a logical low being applied to the match line
20
. In this case, if any one of the CAM cells within a word pull the match line
20
to a logical low, the reference data word is deemed to have a mismatch with the stored word.
Since the number of mismatches are typically much larger than the number of matches, the power consumption resulting from this CAM cell design being implemented within a CAM array is significant due to the logic transitions caused by each mismatch. Further, the transferring of logical highs via the n-channel pass transistors
42
in cases of mismatches can result in less than a full logical high being applied to the gates of the n-channel pull-down transistors
44
, an increased speed of degradation for the n-channel pass transistors
42
due to the hot electron effect, and a decreased transition speed. These problems become more significant as the supply voltages utilized decrease and the size of the fabrication processes used to generate the microelectronic components containing CAMs decrease.
In other common CAM designs, the CAM cells are implemented within a NAND configuration as depicted in
FIG. 1B
, such that the CAM cells are coupled together by a match line
30
. In this case, each CAM cell includes an n-channel chain transistor
34
that is coupled in series with other similar n-channel chain transistors that correspond to other CAM cells within a stored word. Prior to a comparison operation, a first end of the match line is precharged to a logical low with a precharge circuit (not shown). When a comparison operation is initiated, the precharge circuit causes a transition at the first end of the match line from a logical low to a logical high. For each of the CAM cells, if a match occurs between the stored bit within the particular CAM cell and the applied reference bit, one of two n-channel pass transistors
32
pass a logical high to the gate of the n-channel chain transistor
34
within the particular CAM cell. This passed logical high is not a full logical high but initially is approximately a threshold voltage below a full logical high.
If the reference bit applied to the CAM cell adjacent to the precharge circuit corresponds to the stored bit within the particular CAM cell, a boot strapping operation occurs between the gate and drain of the n-channel chain transistor of this CAM cell such that the voltage on the gate of the n-channel chain transistor is increased to a logical high voltage which is greater than a normal full logical high. This in turn results in the transistor passing essentially a full logical high to the drain of the n-channel chain transistor of the adjacent CAM cell. If the remainder of the CAM cells within the word each have their applied reference bit match their stored bit, subsequent boot strapping operations occur along the match line such that eventually a logical high voltage is propagated to a second end of the match line where it can be sensed by a sense circuit (not shown).
This NAND configuration for the CAM cells reduces the power consumption for the CAM compared to the NOR configuration since significant logic transitions only occur during a match, which as stated above is normally less common than a mismatch. One key problem with the well-known NAND configuration as described above with reference to
FIG. 1B
is the need to have a boot strapping operation occur within each of the n-channel chain transistors in order to effectively propagate the logical high to the second end of the match line. The use of boot strapping operations result in a number of disadvantages. For one, the high voltage, which is greater than a normal logical high voltage, generated on the gate of the n-channel chain transistors during a match condition due to the boot strapping operation results in higher than normal degradation rates of the n-channel chain transistors and n-channel pass transistors due to hot electron effects. Further, these high voltages on the gates of the n-channel chain transistors are indefinite and not fully reliable since they are generated through a dynamic condition. This unreliability of the gate voltages decreases the reliability of the high voltages that are passed by the n-channel chain transistors, especially as the supply voltages utilized are being decreased in recent designs. Yet further, the boot strapping operation that occurs within each of the n-channel chain transistors slows the propagation of the logical high significantly and hence reduces the speed of the comparison operation altogether. Even further, in the dynamic situation, there is a drain to source voltage drop through each of the n-channel chain transistors which limits the number of n-channel chain transistors that can be coupled in series and still allow for sensing of the match condition.
The above described problems with the boot strapping operations become increasingly significant in more recent designs in which the supply voltages utilized decrease in voltage levels and the fabrication processes used to generate the microelectronic components containing CAMs decrease in size.
SUMMARY OF THE INVENTION
The present invention is directed to a modified CAM cell design which can be used as supply voltage levels and fabrication process sizes decrease. In preferred embodiments, when a reference bit applied to the CAM cell matches a stored bit, p-channel pass transistors wit
Avramescu Radu
Calin Liviu
Mai Son
Nortel Networks Limited
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