Content addressable memory array having flexible priority...

Details Content addressable memory array having flexible priority... Content addressable memory array having flexible priority...

2006-02-07

2006-02-07

Anderson, Matthew D. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C365S049130

Reexamination Certificate

active

06996662

ABSTRACT:
A method for processing addresses having variable prefix lengths, including (1) applying an input address to a plurality of CAM blocks; (2) assigning different sets of CAM blocks to store prefixes of different lengths; (3) generating a hit signal and an index signal with each of the CAM blocks in response to the input address; (4) programming a plurality of routing values; (5) routing the hit signals to a priority encoder in an order determined by the routing values; (6) generating an output hit signal with the priority encoder in response to the hit signals; (7) selecting one of the routing values as an index routing value in response to the output hit signal; and (8) routing one of the index signals as an output index value in response to the index routing value. Circuitry for implementing the method is also provided.

REFERENCES:
patent: 5467319 (1995-11-01), Nusinov et al.
patent: 6249467 (2001-06-01), Pereira et al.
patent: 6687785 (2004-02-01), Pereira
Article entitled “A Longest Prefix Match Search Engine for Multi-Gigabit IP Processing”, Masayoshi Kobayashi et al., ©2000 IEEE.

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