Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-08-28
2003-01-28
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S724000, C438S675000
Reexamination Certificate
active
06511919
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating semiconductor devices and, more particularly, to a method of forming contacts between adjacent gate lines.
2. Description of the Related Art
In conventional DRAM devices having numerous memory cells, one memory cell stores one bit of information. A memory cell typically consists of a storage capacitor and an access transistor. Either one of source or drain impurity regions of the access transistor is connected to one of the capacitor terminals. The other impurity region and the transistor gate electrode are connected to a bit line and a word line, respectively. In addition, the other capacitor terminal is connected to a reference voltage. It is, therefore, important to provide a proper electrical connection between components of the devices for operation. Such connections between device components can be made by contacts formed in the insulating layer.
With recent advances of semiconductor manufacturing techniques, design rules get smaller and smaller for semiconductor devices. As a result, alignment margin is difficult to secure, especially when aligning contacts between closely spaced conductive lines. Accordingly, for sub-quarter micron semiconductor devices, contacts are formed self-aligned with conductive lines.
The well-known self-aligned contact (SAC) formation process is described as follows. First, gate lines are formed on a semiconductor substrate. Nitride spacers are formed on the sidewalls of the gate lines. An interlayer insulating layer is deposited on the substrate including the gate lines and the spacers. Selected portions of the interlayer insulating layer are etched to form self-aligned contact holes for bit lines and capacitor storage nodes.
FIG. 1A
schematically shows the resulting structure formed in accordance with above-mentioned conventional method, i.e., a top plan view of a semiconductor substrate with a COB (capacitor over bit line) structure. In
FIG. 1A
, reference number
10
denotes a gate line, reference number
12
denotes a bit line, reference number
14
denotes a storage node contact (hereinafter referred to as BC), reference number
16
denotes a bit line contact (hereinafter referred to as DC), reference number
22
denotes an active region and
24
denotes a nitride spacer. In the COB structure, since bit line
12
intersects gate line
10
outside of the active region
22
, DC
16
is formed in the active region and extends out of the active region
22
, thus DC
16
is formed larger than BC
14
in a given area. Also, in a CUB (capacitor under bit line) structure, DC is formed larger than BC because larger contact area is preferably needed to reduce sheet resistance, and BC
14
is more restricted against enlargement of its area than DC is. Accordingly, a spacing between adjacent gate lines where the DC hole is to be formed (hereinafter referred to as the DC forming region) is larger than a spacing between adjacent gate lines where the BC hole is to be formed (hereinafter referred to as the BC forming region), and the layout for the plural adjacent gate line is adjusted to meet these conditions.
FIG. 1B
, a cross-sectional view taken along line I-I′ of
FIG. 1A
, illustrates a problem associated with above-mentioned gate line layout. When an interlayer insulating layer
26
is etched to form the DC and BC holes, several problems can occur. As described above, according to the conventional method, DC has a larger margin than BC. In addition, DC is formed to a dimension larger than BC. The DC hole etching rate is relatively greater than the BC hole etching rate. As a result, the interlayer insulating layer
26
can remain on the substrate of the BC forming region (see reference number
26
a
of
FIG. 1B
, so called “not-opening phenomenon”) due to low BC hole etching rate. On the other hand, the nitride spacer
24
can be over-etched (see inside the circle of the reference number
27
of
FIG. 2
) due to high DC hole etching rate, thereby weakening the top edge portion of the gate lines (weakening the DC shoulder) and, in a severe case, exposing the gate lines. This results in an undesirable electrical bridge between the gate lines and the DC pads.
Accordingly, a method is needed to form SAC openings avoiding the above described not-opening and over-etching problems.
SUMMARY OF THE INVENTION
The present invention provides a method of forming self-aligned contacts between adjacent gate lines for a bit line and a capacitor in a semiconductor device.
According to the present invention, gate lines are formed such that a spacing between adjacent gate lines where a bit line contact hole is to be made is equal to or less than a spacing between adjacent gate lines where a storage node contact is to be made.
According to one embodiment of the present invention, a top dimension of the bit line contact is larger than a top dimension of the storage node contact.
In accordance with another embodiment of the present invention, a method of forming self-aligned contacts between adjacent gate lines in a semiconductor device is provided. The method includes forming a gate electrode layer on a semiconductor substrate. The gate electrode layer is etched to form a plurality of spaced apart gate lines. A spacing between adjacent gate lines where a bit line contact is to be made is equal to or less than a spacing between gates where a storage node contact is to be made. A nitride layer is formed on the semiconductor substrate including the gate lines. The nitride layer is then etched to form a nitride spacer on a sidewall of each of the gate lines. An oxide layer is formed to fill spaces between the gate lines. The oxide layer is etched to form a bit line contact hole and a storage node contact hole. A top dimension of the bit line contact is larger than a top dimension of the storage node contact.
The method may further include forming a second nitride layer after the formation of the nitride spacer.
Preferably, the spacing between adjacent gate lines where a bit line contact is to be made is in the range of about 0.05 to 0.3 microns and the spacing between adjacent gate lines where storage node contact is to be made is in the range of about 0.1 to 0.4 microns.
The top dimension of the storage node contact is in the range of about 0.28 micron×0.5× to 0.28 micron×0.5 to 0.28 micron×1×0.28 micron×1 and the top dimension of the bit line contact is in the range of about 0.28 micron×0.5×0.48 micron×0.5 to 0.28 micron×1×0.48 micron×1.
In accordance with yet another embodiment of the present invention, a method of forming self-aligned contacts between adjacent gate lines in a semiconductor device is provided. The method includes forming a gate electrode layer on a semiconductor substrate. The gate electrode layer is etched to form a plurality of spaced apart gate lines. A spacing between adjacent gate lines where a bit line contact is to be made is equal to or less than a spacing between adjacent gate lines where a storage node contact is to be made. A nitride layer is formed on the semiconductor substrate including the gate lines. An oxide layer is formed on the nitride layer to fill spaces between the gate lines. The oxide layer and the nitride layer are etched to form a bit line contact hole and a storage node contact hole while concurrently forming a nitride sidewall spacer on a sidewall of each of the gate lines. A top dimension of the bit line contact is larger than a top dimension of the storage node contact. Preferably, a spacing between adjacent gate lines where a bit line contact is to be made is in the range of about 0.05 to 0.3 microns and a spacing between adjacent gate lines where a storage node contact is to be made is in the range of about 0.1 to 0.4 microns.
In a preferred embodiment of the present invention, the top dimension of the storage node contact is in the range of about 0.28 micron×0.5×0.28 micron×0.5 to 0.28 micron×1×0.28
Lee Won-Sung
Park Young-Woo
Le Dung A
Marger & Johnson & McCollom, P.C.
Nelms David
Samsung Electronics Co,. Ltd.
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