Contactless tite RAM

Details Contactless tite RAM Contactless tite RAM

1983-06-17

1985-10-01

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

365185, 357 41, G11C 1140

Patent

active

045450340

ABSTRACT:
A transversly injected quasi-floating gate memory cell. A memory transistor in bulk silicon has a channel region in bulk silicon which is capacitatively coupled both to a thin polysilicon quasi-floating gate and to an overlying word line. The thin polysilicon level which comprises the floating gate is not coterminous with the channel region of the memory transistor, but the quasi-floating gate portion of the thin polysilicon layer is connected, through a polysilicon channel region, to a write bit line. The overlying word line thus addresses both the write transistor in a thin polysilicon level and also the memory transistor itself in the substrate.

REFERENCES:
patent: 4105475 (1978-08-01), Jenne
patent: 4380804 (1983-04-01), Lockwood et al.

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