Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-12-27
2004-03-09
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S316000, C257S321000, C365S185100, C365S185130, C365S185170
Reexamination Certificate
active
06703661
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related generally to a non-volatile semiconductor memory array and its fabrication methods, and more particularly, to a contactless NOR-type non-volatile semiconductor memory array and its fabrication methods for high-density mass storage applications.
DESCRIPTION OF THE RELATED ART
A semiconductor memory is in general organized in a matrix form having a plurality of rows perpendicular to a plurality of columns. The intersection of one row and one column has a storage element called a memory cell and each memory cell is capable of storing a binary bit of data. Each of the plurality of rows represents a word line and each of the plurality of columns represents a bit line. A decoder system including a row decoder block and a column decoder block is used to generate the binary-coded input in order to select the desired row or column for a write or read operation. Basically, the speed*power*density product is a figure of merits for evaluating the performance of a semiconductor memory. In general, the cell size is a major concern for high-density mass storage applications; the RC delay time of the word line and the bit line is a major concern for high-speed write or read operation; and the operation current and voltage during a write or a read is a major concern for operation power.
A flash memory is in general organized in a NAND-type configuration or a NOR-type configuration. A NAND-type flash array having a byte of cells formed in series with sharing source/drain diffusion regions has a density that is about twice of a NOR-type flash array. However, the access time is slow for a NAND-type array due to the series-connected nature of cells and, therefore, a NAND-type array is limited to 16 cells in series in order to avoid excessive series resistance. Moreover, a NAND-type array is in general programmed by Fowler-Nordheim tunneling between the overlapping area of a drain diffusion region of a cell and its floating gate and the programming speed of a NAND-type array is relatively slow as compared the hot-electron injection used often by a NOR-type array. In additions a high-voltage is needed to be applied to the word lines of the unselected cells, the complicated support circuits are required for a NAND array. Therefore, the only advantage of a NAND-type array is the density and the cell size can be made to be 4F
2
(2F×2F), where F is the minimum-feature-size of technology used.
A typical NOR-type array is shown in
FIG. 1
, where
FIG. 1A
shows a simplified top plan view of a 2×2 array;
FIG. 1B
shows a schematic circuit diagram of
FIG. 1A
;
FIG. 1C
shows a cross-sectional view along A-A′ direction in
FIG. 1A
; and
FIG. 1D
shows a cross-sectional view along B-B′ direction in FIG.
1
A. Now, referring to
FIG. 1A
, the active region of a NOR-type array is defined and formed on a p-semiconductor substrate
10
and the isolation region (outside of the active region) is formed with a thicker field-oxide layer (FOX), in which a larger active region is defined for forming a contact. A thin tunneling-oxide layer is formed over the active region, then a floating-gate (FE) made of doped polycrystalline silicon is formed over the thin tunneling-oxide layer and the field-oxides (FOX) and is patterned to have a portion remained on the field-oxides to increase the coupling ratio of the floating-gate, as shown in FIG.
1
D. An intergate dielectric layer of the oxide-nitride-oxide (ONO) structure is formed over the patterned floating-gate layer and the field-oxides, then a control-gate (CG) layer is formed over the intergate dielectric layer and is patterned to form the word lines (WL) and the stack-gate regions of the cells, as shown in FIG.
1
A and FIG.
1
C. The no source/drain diffusion regions are formed in a self-aligned manner in the semiconductor substrate
10
by using the patterned word lines as an implantation mask, as shown in
FIG. 1C. A
tick interlayer dielectric layer made of oxide is formed over the structure and is planarized, then the contact holes are open and filled with the metal plugs, as shown
FIG. 1C. A
metal film is deposited over the planarized structure and is then patterned to form the bit lines (BL) perpendicular to the word lines, as shown in FIG.
1
A and
FIG. 1C
, in which each of the bit lines is electrically connected to the drain diffusion regions of the cells in a column through the contact holes being filled with the metal plugs. As shown in
FIG. 1A
, the unit cell area as marked by the dash line is at least 8F
2
if the space between the contact and the word line is F. It is quite clear that the contact in a cell of a NOR-type array becomes a major obstacle for reducing the cell size.
It is therefore an object of the present invention to provide a contactless NOR-type non-volatile memory array with a much reduced cell size.
It is another object of the present invention to provide methods of making a contactless NOR-type non-volatile memory array with a cell size of 4F
2
.
SUMMARY OF THE INVENTION
A contactless NOR-type memory array and its fabrication methods are disclosed by the present invention. A contactless NOR-type memory array comprises: a plurality of parallel isolation regions being formed alternately on a semiconductor substrate of a first conductivity type with a plurality of active regions formed therebetween, wherein in a raised field-oxide film is formed on each of the plurality of parallel isolation regions and a thin tunneling-dielectric layer is formed on each of the plurality of active region; a plurality of word lines being formed alternately and transversely to the plurality of parallel isolation regions, wherein each of the plurality of word lines comprises an elongated control-gate layer being sandwiched between an interlayer dielectric layer formed on the top and an intergate dielectric layer formed at the bottom, and a plurality of integrated floating-gate layers being formed beneath the intergate dielectric layer, wherein each of the plurality of integrated floating-gate layers comprises a major floating-gate layer being formed on the thin tunneling-dielectric layer and two extended floating-gate layers being formed separately on a portion of each of two nearby raised field-oxide films; a plurality of common-source diffusion regions being formed along the common-source lines and a plurality of common-drain diffusion regions being formed along the common-drain lines; a plurality of dielectric spacers being formed over the sidewalls of each of the plurality of word lines, wherein the raised field-oxide films along each of the common-source lines are etched to set up a flat bed formed alternately by the common-source diffusion regions and the etched field-oxide films; a silicided common-source conductive layer being formed between a pair of dielectric spacers and over a flat bed with a second thick-oxide layer formed on the top; a silicided common-drain conductive island being formed between another pair of dielectric spacers and on each of the plurality of common-drain diffusion regions and a portion of two raised field-oxide films formed nearby; and a plurality of bit lines being formed transversely to the plurality of word lines having each of the plurality of bit lies formed over a flat surface formed alternately by second thick-oxide layer, interlayer dielectric layer, and silicided common-drain conductive islands, wherein each of the plurality of bit lines comprises a hard masking layer being formed on a metal layer to simultaneously pattern and form the metal layer and said silicided common-drain conductive islands along each of the plurality of bit lines.
The plurality of parallel isolation regions can be formed by using either shallow-trench-isolation (STI) technique or local-oxidation of silicon (LOCOS) techniques; the elongated control-gate layer is preferably a composite conductive layer having a refractory-metal silicide layer formed over a doped polycrystalline-silicon layer; the interlayer dielectric layer is preferably a composite die
Dickinson Wright PLLC
Jackson Jerome
Landau Matthew C.
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