Contact system for wafer level testing

Details Contact system for wafer level testing Contact system for wafer level testing

2007-02-13

2007-02-13

Nguyen, Vinh P. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB

Reexamination Certificate

active

10819673

ABSTRACT:
Disclosed herein are exemplary embodiments of a contact system (referred to as a “Z-block”) for interfacing a semiconductor wafer to an electrical tester, and methods for making the same. In a preferred embodiment, the Z-block comprises three stacked pieces or layers: an upper and lower piece which are similar in structure, and a unique middle piece. The pieces each contain corresponding locking holes and probe pin holes. The locking holes are strategically arranged on each of the pieces to allow the stacked piece structure to be locked together at various points during its manufacture. After alignment of the probe pin holes in the various pieces, probe pins are injected into these holes. The probe pins are then aligned and locked into place by moving the middle piece relative to the upper and lower pieces. Such locking of the probe pins is accomplished through interaction of the middle piece with the shape of the probe pins, which prevents the probe pins from slipping out of the probe pin holes.

REFERENCES:
patent: 4423376 (1983-12-01), Byrnes et al.
patent: 4506215 (1985-03-01), Coughlin
patent: 4622514 (1986-11-01), Lewis
patent: 6404211 (2002-06-01), Hamel et al.

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