Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-04-12
2002-11-26
Chaudhuri, Olik (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S534000, C257S775000, C438S387000, C438S398000, C438S620000
Reexamination Certificate
active
06486531
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a contact structure in a semiconductor device including a dynamic random access memory (DRAM) with a capacitor, and a method of forming the same.
2. Description of the Related Art
As the integration density of semiconductor devices increases, the area of a capacitor, which is an information storage unit of a memory device, e.g. DRAM, decreases. To obtain capacitance equal to or larger than that before on the decreased area, methods for increasing the area of an effective electrode by making the electrode of the capacitor in a three-dimensional shape such as a cylinder or a pin have been used. However, as the height of an electrode of a capacitor increases, a global step difference between a cell array area in which the capacitor is formed and a peripheral circuit area or a logic circuit area for driving memory cells increases. This global step difference causes many problems during a subsequent metal wiring process. In particular, in the case of a Merged DRAM with Logic (MDL) device, the number of layers of a metal interconnection is larger as compared with a simple DRAM device, so the problem of a global step difference is more serious.
To reduce the global step difference between a cell array area and a peripheral circuit area or a logic circuit area, a method of leaving a sacrificial oxide layer used for forming a lower electrode without removing it from the peripheral circuit area or the logic circuit area may be used. This method will be described with reference to
FIG. 1. A
reference character A in
FIG. 1
denotes a cell array area in a DRAM, and a reference character B denotes a peripheral circuit area or a logic circuit area.
Referring to
FIG. 1
, a capacitor composed of a lower electrode
40
, a dielectric layer
50
and an upper electrode
60
is formed in a cell array area A of the DRAM. An interlayer dielectric layer
10
is interposed between the lower electrode
40
and a substrate (not shown) including a transistor (not shown). The lower electrode
40
is connected to an active region of the substrate through a lower electrode contact plug
20
. Metal contacts
90
,
92
and
94
connected to the upper electrode
60
, a predetermined active region of the substrate and a circuit device
62
such as a load resistance, respectively, are formed in a peripheral circuit area or a logic circuit area B. Here, the lower electrode
40
is formed to be as high as possible in a cylinder shape to increase an effective area thereof. The outer surface of the cylinder-shape lower electrode
40
is surrounded by a sacrificial oxide layer, that is, a mold insulation layer
30
, and is not used as an effective electrode. When even the outer surface of the lower electrode
40
is used as an electrode after the mold insulation layer
30
is removed, global step difference as much as the height of the lower electrode
40
occurs between the cell array area A and the peripheral circuit area or the logic circuit area B.
As a result of leaving the mold insulation layer
30
, when interlayer dielectric layers
70
,
30
and
10
are etched to form contact holes
80
,
82
and
84
for the metal contacts
90
,
92
and
94
in the peripheral circuit area or the logic circuit area B, the difference between the depth of a deep contact hole, for example, the contact hole
82
for the metal contact
92
connected to the active region of the substrate, and the depth of each of the contact holes
80
and
84
for the upper electrode contact
90
and the circuit device contact
94
, respectively, is very large. Accordingly, when the contact holes
80
and
84
exposing the upper electrode
60
and the circuit device
62
, respectively, which are formed of conductive material such as doped polysilicon, are formed, etching may not be stopped at the upper electrode
60
and the circuit device
62
but may proceed to penetrate the upper electrode
60
and the circuit device
62
. When the contact holes
80
and
84
penetrate the upper electrode
60
and the circuit device
62
, and thus the metal contacts
90
and
94
are formed even in the underlying mold insulation layer
30
, contact resistance increases, and the distribution of resistance values is large. In other words, the resistance values are non-uniform. In the worst case, the metal contacts
90
and
94
may be short-circuited with other interconnections passing therebelow.
SUMMARY OF THE INVENTION
To solve the above problems, it is a first object of the present invention to provide a contact structure that realizes a satisfactory contact profile in a peripheral circuit area or a logic circuit area and does not penetrate an underlying interconnection in a semiconductor device including a dynamic random access memory (DRAM).
It is a second object of the present invention to provide a method of forming the above contact structure.
Accordingly, to achieve the first object of the invention, there is provided a contact structure formed in a peripheral circuit area or a logic circuit area of a semiconductor device including a DRAM having a cell array area with a plurality of DRAM cells and the peripheral or logic circuit area. The contact structure includes a lower interconnection formed of the same material as a capacitor upper electrode of each of the plurality of DRAM cells, an interlayer dielectric layer formed on the lower interconnection and having a contact hole exposing a predetermined region of the lower interconnection, and an upper interconnection formed on the interlayer dielectric layer, filling the contact hole and electrically connected to the lower interconnection. The lower portion of the lower interconnection has a larger area than the bottom of the contact hole and extends downward so that the lower interconnection has a T-shape in a cross-sectional view.
To achieve the second object of the invention, in one aspect, there is provided a method of forming a contact structure in a peripheral circuit area or a logic circuit area of a semiconductor device including a DRAM having a cell array area with a plurality of DRAM cells and the peripheral or logic circuit area. First, capacitor upper electrode of each DRAM cell is formed, and concurrently, a lower interconnection of the same material as the capacitor upper electrode is formed to have a T-shape in cross section on a predetermined portion of the peripheral circuit area or the logic circuit area. Next, an interlayer dielectric layer is formed on the lower interconnection to have a contact hole exposing a predetermined portion of the lower interconnection. An upper interconnection is formed on the interlayer dielectric layer to fill the contact hole and be electrically connected to the lower interconnection. Therefore, the contact structure is completed.
In another aspect, there is provided a method of forming a plurality of contact structures having contact holes of different depths in a peripheral circuit area or a logic circuit area of a semiconductor device including a DRAM having a cell array area with a plurality of DRAM cells and the peripheral or logic circuit area. Firstly, a mold insulation layer is formed on the surface of a substrate including a capacitor lower electrode contact plug of each DRAM cell. The mold insulation layer is patterned, thereby forming a lower electrode opening exposing the capacitor lower electrode contact plug and a lower interconnection opening where a contact structure having a relatively shallow contact hole among the plurality of contact structures will be formed. Subsequently, a lower electrode layer is formed by depositing a conductive material on the entire surface of the mold insulation layer and the openings. A cylinder-shape capacitor lower electrode is formed within the lower electrode opening, and simultaneously, a cylinder-shape dummy lower electrode pattern is formed within the lower interconnection opening, by removing the lower electrode layer deposited on the mold insulation layer. Nex
Chaudhuri Olik
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Smoot Stephen W.
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