Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Including integrally formed optical element
Reexamination Certificate
2006-10-03
2006-10-03
Brewster, William M. (Department: 2823)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Including integrally formed optical element
C438S129000, C438S149000, C438S672000
Reexamination Certificate
active
07115433
ABSTRACT:
First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer including a lower layer of Cr and an upper layer of aluminum-based material is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and a thermal treatment process using annealing step is executed. At this time, all or part of aluminum oxide (AlOx) layer having a high resistivity, which is formed on the gate wire and/or the data wire during manufacturing process, may be removed. Then, the passivation layer is patterned to form contact holes exposing the drain electrode, the gate pad and the data pad, respectively. Next, IZO is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad, respectively. By removing aluminum oxide (AlOx) layer having a high resistivity, through annealing step, the contact resistance between the metal of aluminum-based material, and IZO may be minimized, because they directly contact each other.
REFERENCES:
patent: 5478766 (1995-12-01), Park et al.
patent: 5776804 (1998-07-01), Hayashi
patent: 6072450 (2000-06-01), Yamada et al.
patent: 6222595 (2001-04-01), Zhang et al.
patent: 6278502 (2001-08-01), Colgan et al.
patent: 6531392 (2003-03-01), Song et al.
patent: 2002/0061410 (2002-05-01), Sasaki et al.
patent: 1998-079255 (1998-11-01), None
patent: 1999-0077818 (1999-10-01), None
Silicon Processing for the VLSI Era; vol. 1: Process Technology; Stanley Wolf, Ph.D.; Lattice Press; 1986; pp. 191-195.
Brewster William M.
F. Chau & Associates LLC
Samsung Electronics Co,. Ltd.
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