Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Beam leads
Reexamination Certificate
2002-06-24
2004-02-24
Lebentritt, Michael S. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Beam leads
C257S696000, C257S738000, C257S758000, C257S778000, C257S784000
Reexamination Certificate
active
06696757
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related in general to the field of semiconductor devices and processes and more specifically to the structure of metallurgical interconnection pads for flip-chip assembly of semiconductor chips.
DESCRIPTION OF THE RELATED ART
The structure of contact pad metallizations and solder bumps for connecting integrated circuit (IC) chips to semiconductor packages or outside parts, as well as the thermomechanical stresses and reliability risks involved, have been described in a series of detailed publications by the International Business Machines Corporation in 1969 (IBM J. Res. Develop., Vol. 13, pp. 226-296): P. A. Totta et al., SLT Device Metallurgy and its Monolithic Extension, L. F. Miller, Controlled Collapse Reflow Chip Joining, L. S. Goldmann, Geometric Optimization of Controlled Collapse Interconnections, K. C. Norris et al., Reliability of Controlled Collapse Interconnections, S. Oktay, Parametric Study of Temperature Profiles in Chips Joined by Controlled Collapse Techniques, B. S. Berry et al., Studies of the SLT Chip Terminal Metallurgy.
During and after assembly of the IC chip to an outside part such as a substrate or circuit board by solder reflow, and then during device operation, significant temperature differences and temperature cycles appear between semiconductor chip
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and the substrate. The reliability of the solder joint is strongly influenced by the coefficients of thermal expansion of the semiconductor material and the substrate material. For example, there is more than one order of magnitude difference between the coefficients of thermal expansion of silicon and FR-4. This difference causes thermomechanical stresses, which the solder joints have to absorb. Detailed calculations, in the literature cited above and in other publications of the early 1980's, involving the optimum height and volume of the solder connection and the expected onset of fatigue and cracking proposed a number of solder design solutions.
The fabrication methods and reliability problems involving flip-chips re-appear in somewhat modified form for ball-grid array packages. In their book “Chip Scale Package” (McGraw-Hill, 1999), John H. Lau and Shi-Wei Ricky Lee describe various semiconductor devices and packages of contemporary “chip-scale” families, as they are fabricated by a number of semiconductor companies worldwide. The newest designs and concepts in microelectronics assembly and packaging are aiming for a package with a planar area not substantially greater than the silicon chip itself, or at most 20% larger area. This concept, known as Chip-Scale Package (CSP), is finding particular favor with those electronics industries where the product size is continually shrinking such as cellular communications, pagers, hard disk drivers, laptop computers and medical instrumentation. Most CSP approaches are based on flip-chip assembly with solder bumps or solder balls on the exterior of the package, to interface with system or wiring boards.
The chip-to-be-flipped may be attached to a second interconnection surface such as an interposer, or alternatively, coupled directly to a printed circuit board (PCB). Attaching the flip-chip to the next interconnect is carried out by aligning the solder bumps or balls on the chip to contact pads on the second level interconnection and then performing a second solder reflow operation. During the reflow, the bumps or balls liquefy and make a bond to the next interconnect level which has pads or traces to receive the solder. Following the solder reflow step, flip-chips often use a polymeric underfill between the chip and the interposer or PCB to alleviate mechanical stress caused by the mismatch in the coefficients of thermal expansion (CTE) between the semiconductor chip, the interposer, if any, and the PCB. Many reliability problems occur due to the stress placed on the solder bumps or balls when the integrated circuit is cycled from hot to cool during operation. When another set of solder balls on the opposite side of the interposer is employed to complete the bonding process to a PCB, this second set may also be affected by similar stress and reliability problems.
One method aims at absorbing part of the thermomechanical stress on the solder joints by plastic material surrounding the joints and filling the gap between chip and substrate. See for instance, U.S. Pat. No. 6,228,680, issued on May 8, 2001; U.S. Pat. No. 6,213,347, issued on Apr. 10, 2001, and U.S. Pat. No. 6,245,583, issued on Jun. 12, 2001 (Thomas et al., Low Stress Method and Apparatus for Underfilling Flip-Chip Electronic Devices). However, the underfilling method represents an unwelcome process step after device attachment to the motherboard.
Another method applies a polymer layer on top of the protective overcoat with the aim of reducing the stress to the overcoat perimeter and the dielectric material underlying the contact pad. See for instance the publication “A Silicon and Aluminum Dynamic Memory Technology” by Richard A. Larsen (IBM J. Res. Develop., vol.24, May 1980, pp. 268-282). The article includes description of a flip-chip packaging technology using a solder bump on an under-bump metallization, which is resting its perimeter on a thick polyimide layer. The bump structure is often supported by another polyimide layer.
An urgent need has arisen for a coherent, low-cost method of fabricating flip-chip assembly of semiconductor devices offering a fundamental metallurgical solution of solder-to-metal interconnection and thermomechanical stress reliability. The method should be flexible enough to be applied for different semiconductor product families and a wide spectrum of design and process variations. Preferably, these innovations should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.
SUMMARY OF THE INVENTION
A metallurgical interconnection for electronic devices is described, wherein the interconnection has first and second interconnection metals. The first metal is shaped to enlarge the contact area, thus providing maximum mechanical interconnection strength, and to stop nascent cracks, which propagate in the interconnection. Preferred shapes include castellation and corrugation. The castellation may include metal protrusions, which create wall-like obstacles in the interconnection zones of highest thermomechanical stress, whereby propagating cracks are stopped. The surface of the first metal has an affinity to form metallurgical contacts. The second metal is capable of reflowing. The first metal is preferably copper, and the second metal tin or a tin alloy.
The present invention is related to chip-scale packages, especially those fabricated with plastic multi-level substrates having a plurality of contact pads for solder “ball” board attach. Copper is the preferred metal used in constructing these substrates.
The present invention is further related to high density and high speed ICs with copper interconnecting metallization, especially those having high numbers of metallized inputs/outputs for flip-chip assembly. These circuits can be found in many device families such as processors, digital and analog devices, logic devices, high frequency and high power devices, and in both large and small area chip categories.
It is an aspect of the present invention to drastically reduce the number of solder joint failures in semiconductor packages and flip-chip devices by changing the failure mechanism from a probabilistic weakest-link mode to a parallel-type mode. In known technology, solder joint cracks, initiated by thermomechanical stress and implied with enough energy, are able to migrate until they find the weakest link in the joint and delaminate the joint. The failure mechanism is, therefore, controlled by the probability that a nascent crack will find the weakest link.
According to the Griffith energy-balance concept for crack formation in brittle solids (first published in 1920), a change in the length of a nascent crack or notch cannot change the sum of a
Coyle Anthony L.
Yunus Mohammad
Brady III Wade James
Lebentritt Michael S.
Menz Doug
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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