Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
2000-01-25
2003-07-22
Baxter, Janet (Department: 1752)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S311000, C430S005000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06596466
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the fabrication of semiconductor devices, and more particularly the formation of contact structures in a semiconductor device.
BACKGROUND OF THE INVENTION
Integrated circuits can typically include various layers of conductive, semiconductive, and/or insulating materials. For example, an integrated circuit may include a substrate in which a number of active devices (such as transistors) may be formed. Gates for insulated gate field effect transistors may be formed from a deposited semiconductor material. Such active devices. may then be connected to one another by one or more conductive or semiconductive layers. The interconnecting conducting layers may be separated from one another by insulating layers.
Insulating layers typically provide electrical isolation between conductive and/or semiconductive layers. Conductive or semiconductive layers may be formed from a single layer of material, or alternatively, include one or more conductive (or semiconductive) materials.
Different conductive or semiconductive layers can be connected to one another by contacts and/or vias. Contacts and/or vias can include contact holes that extend through one or more insulating layers. Conventionally, contacts can connect a substrate to a conductive or semiconductive layer, while a via can connect two different conductive or semiconductive layers to one another.
Layers may be patterned by lithography and etch steps. For example, a lithography step can form an interconnect etch mask over a conductive and/or semiconductive layer. An etch step can then transfer the interconnect etch mask pattern to the conductive and/or semiconductive layer. A lithography step can also form a contact hole etch mask over an insulating layer. An etch step can then form a contact hole through the insulating layer.
One concern with certain contact structures can be the alignment of a contact with a lower conductive and/or semiconductor layer. Because a contact can be formed by etching a hole through an insulating layer to an underlying conductive or semiconductive layer, it is desirable for the etched hole to be situated directly over the desired contact location in the lower conducting layer. However, because the sizes of features in modern integrated circuits can be so small, some misalignment can be inherent in a manufacturing process.
Another concern with certain contact structures can be the alignment of an intermediate layer with respect to an underlying layer. As but one example, a contact hole may have to be formed adjacent to, or overlap, a transistor gate layer. In the event such a gate is misaligned with respect to an underlying layer, the available area exposed by a contact hole can be reduced.
Yet another concern with certain contact structures can be variations in the dimensions of an intermediate layer. As but one example, a transistor gate layer may have a certain critical dimension (CD) range. In the event such a gate layer is at the high end of such a range, the gate layer may cover more available contact area than nominal or low CD ranges. This can be exacerbated by complex gate structure shapes. Many times, complex gate structure shapes can contribute to increasing the compactness of a circuit.
A number of examples will now be described to further illustrate the effect of misalignment and CD variations on the formation of certain contacts.
FIGS. 10A and 10B
are top plan views showing an example of a conventional mask set and a corresponding contact formation method. In particular,
FIG. 10A
shows three overlapping mask patterns, each distinguished by a particular hatching pattern.
A first mask is an “active” mask
1000
. An active mask
1000
can be used to form an “active” area in a substrate. For example, an active mask
1000
can be used to form isolation structures, such as shallow trench isolation (STI) structures or those formed with local oxidation of silicon (LOCOS) methods.
A second mask can be a gate mask
1002
. A gate mask
1002
can be used form a gate layer pattern over an active area. A gate mask
1002
may pattern a layer that forms the gate of a transistor. Such a layer may inherently connect two or more transistor gates and/or connect a transistor gate to the substrate (by a “buried” contact or another such contact).
FIG. 10A
also includes a contact hole mask
1004
. A contact hole mask
1004
can be used to form a contact hole to a substrate. (or another conductive layer). The particular contact hole mask
1004
of
FIG. 10A
can be for a “self-aligned” contact. A self-aligned contact may eliminate a minimum spacing requirement from a gate mask
1002
.
FIGS. 10A and 10B
also include a direction indicator that shows a Y direction and an X direction. The Y and X directions are perpendicular to one another.
FIG. 10B
shows an example of a semiconductor device that can be formed with the masks of FIG.
10
A.
FIG. 10B
shows a substrate
1006
that can include active areas
1008
formed therein. A gate layer structure
1010
may be formed on a substrate
1006
and over portions of active areas
1008
. It is noted that a misalignment of the gate layer structure
1010
with respect to the contact hole mask
1004
in the positive Y direction can reduce overall available contact area, as a resulting gate layer structure
1010
can extend into a contact hole
1012
location.
Variations in gate layer structure
1010
CDs can also impact contact area. For example, a gate layer structure
1010
with a high CD can extend into a contact hole location, reducing contact area.
Misalignment between a contact hole mask
1004
and active areas
1008
can also impact contact area. In the example of
FIGS. 10A and 10B
, a misalignment of a contact hole mask
1004
with respect to an active area
1008
in the positive or negative X direction can reduce overall available contact area, as a resulting contact hole
1012
can overlap isolation regions in a substrate
1006
.
FIGS. 10A and 10B
also show one example of how a mask pattern transfers to an underlying device structure. For example, while a contact hole mask
1004
may have a square shape, “edge” and/or “corner” lithography and etch effects can give rise to a resulting contact hole
1012
with a circular shape. Further, while a gate mask
1002
may include sharp stepped features, such as those shown as item
1014
in
FIG. 10A
, such features can be smoothed out in a lithography and etch step, resulting in a more gradually contoured structure, such as the gate layer structure
1010
of FIG.
10
B.
A second conventional example of a mask set and contact formation method are shown in
FIGS. 11
,
12
A to
12
C and
13
A to
13
C.
FIG. 11
is an example of a mask set that may be used to form a “cactus” contact hole.
FIGS. 12A
to
12
C are top plan views illustrating a semiconductor structure that may be manufactured with the mask set of FIG.
11
.
FIGS. 13A
to
13
C are side cross-sectional views corresponding to the views of
FIGS. 12A
to
12
C.
A cactus contact hole can be a contact hole formed adjacent to a cactus shaped intermediate structure. An intermediate structure can potentially extend into a contact hole location, reducing overall contact area. A cactus structure can include a first portion that extends in one direction and a second portion that extends from the first portion at an angle. A cactus contact derives its name from the shape of the intermediate structure, which can, in some configurations, resemble a Saguaro-type cactus. A first portion may correspond to a cactus body while a second portion may correspond to a cactus arm.
A cactus contact hole can be a contact hole that is formed between a body portion and an arm portion of a cactus shaped intermediate structure.
FIG. 11
shows three overlapping mask patterns, each distinguished by a particular hatching pattern. The masks can include an “active” mask
1100
, a gate layer mask
1102
, and a contact hole mask
1104
. A gate layer mask
1102
includes a first section
1106
that extends in the vertical direction of
Pohland Oliver
Wong Kaichiu
Baxter Janet
Cypress Semiconductor Corporation
Lee Sin J.
Sako Bradley T.
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