Contact resistance and capacitance for semiconductor devices

Details Contact resistance and capacitance for semiconductor devices Contact resistance and capacitance for semiconductor devices

2006-05-24

2008-10-21

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07441218

ABSTRACT:
A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout.

REFERENCES:
patent: 6519745 (2003-02-01), Srinivas et al.
patent: 6567967 (2003-05-01), Greidinger et al.
patent: 6609235 (2003-08-01), Ramaswamy et al.
patent: 6815982 (2004-11-01), Buhr
patent: 7124386 (2006-10-01), Smith et al.
patent: 7328419 (2008-02-01), Vuong et al.

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