Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2002-03-06
2003-09-23
Whitehead, Jr., Carl (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257S306000, C257S311000
Reexamination Certificate
active
06624525
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, in particular, characterized by a stack structure of insulating layers which permits formation of minute via-holes without defects through a low-temperature process in a semiconductor highly-integrated circuit device such as a hybrid system LSI including a DRAM (Dynamic Random Access Memory).
2. Description of the Related Art
In recent progress of integration of semiconductor integrated circuit devices, SAC (Self-Align Contact) method, MDC (Modified Contact) method, PSC (Poly Shrink Contact) method, etc., are known for forming a minute via-hole in the manner that an opening portion is formed in an insulating layer interposed between interconnection layers. These methods of forming via-holes will be described below with reference to
FIGS. 1A through 1C
to
FIGS. 4A through 4C
.
First, a conventional SAC process will be described with reference to
FIGS. 1A through 1C
.
Referring first to
FIG. 1A
, interconnection lines
52
for, e.g., bit lines, are formed on an insulating underlayer
51
made of, e.g., SiO
2
, according to a design rule of 0.16 &mgr;m/0.24 &mgr;m for line/space. A SiN film is then formed by deposition, and anisotropically etched to form spacers
54
.
In this case, for surely forming a certain space between the interconnection lines
52
, the thickness of the SiN film must be 0.12 &mgr;m or less.
Note that, on the upper surface of each interconnection line
52
, another SiN film
53
has been formed prior to the formation of the above-described SiN film. Besides, an electrode plug (not shown) has been provided at the portion in the insulating underlayer
51
corresponding to the space between the interconnection lines
52
.
A thick insulating interlayer
55
made of, e.g., BPSG, is then formed on the entire surface by deposition. The surface of the insulating interlayer
55
is flattened through a CMP (Chemical Mechanical Polishing) or etch-back process. A resist pattern (not shown) for 0.24 &mgr;m-wide via-holes is formed using a photolithographic technique. Anisotropic etching is carried out using the SiN films
53
and the spacers
54
, as etching stoppers, to form a via-hole
56
.
Referring next to
FIG. 1B
, a thick amorphous Si layer
57
doped with, e.g., P (phosphorus), is formed on the entire surface by deposition.
Referring next to
FIG. 1C
, polishing by CMP method is carried out until the surface of the insulating interlayer
55
is exposed. The part of the doped amorphous Si layer
57
formed on the insulating interlayer
55
is thereby removed to form a Si plug
58
filling in the via-hole
56
. Next, a conventional MDC process will be described with reference to
FIGS. 2A through 2D
.
Referring first to
FIG. 2A
, interconnection lines
52
for, e.g., bit lines, are formed on an insulating underlayer
51
made of, e.g., SiO
2
, according to a design rule of 0.16 &mgr;m/0.24 &mgr;m for line/space. A thick insulating interlayer
55
made of, e.g., BPSG, is then formed on the entire surface by deposition. The surface of the insulating interlayer
55
is flattened through a CMP or etch-back process. A resist pattern (not shown) for 0.24 &mgr;m-wide via-holes is formed using a photolithographic technique. Anisotropic etching is carried out using the interconnection lines
52
as etching stoppers, to form a via-hole
56
.
An electrode plug (not shown) has been provided at the portion in the insulating underlayer
51
corresponding to the space between the interconnection lines
52
.
Referring next to
FIG. 2B
, an insulating film
59
made of, e.g., SiN, having an etching selectivity to the BPSG film, is formed by deposition.
In this case, for surely forming a certain space between the interconnection lines
52
in the subsequent anisotropic etching process, the thickness of the insulating film
59
must be 0.12 &mgr;m or less, in particular, 0.1 &mgr;m or less.
Referring next to
FIG. 2C
, anisotropic etching is carried out to form spacers
60
, which newly define a via-hole
61
between them.
Referring next to
FIG. 2D
, a thick amorphous Si layer doped with, e.g., P (phosphorus), is formed on the entire surface by deposition. Polishing by CMP method is then carried out until the surface of the insulating interlayer
55
is exposed. The part of the doped amorphous Si layer formed on the insulating interlayer
55
is thereby removed to form a Si plug
62
filling in the via-hole
61
.
Next, a conventional PSC process will be described with reference to
FIGS. 3A through 3C
and
4
A through
4
C.
Referring first to
FIG. 3A
, interconnection lines
52
for, e.g., bit lines, are formed on an insulating underlayer
51
made of, e.g., SiO
2
, according to a design rule of 0.16 &mgr;m/0.24 &mgr;m for line/space. A thick insulating interlayer
55
made of, e.g., BPSG, is then formed on the entire surface by deposition. The surface of the insulating interlayer
55
is flattened through a CMP or etch-back process. An amorphous Si layer
63
having an etching selectivity to the insulating interlayer
55
is then formed on the entire surface by deposition, into a thickness of, e.g., 0.3 &mgr;m.
An electrode plug (not shown) has been provided at the portion in the insulating underlayer
51
corresponding to the space between the interconnection lines
52
.
Referring next to
FIG. 3B
, a resist pattern (not shown) for 0.24 &mgr;m-wide via-holes is formed using a photolithographic technique. Anisotropic etching is then carried out using the insulating interlayer
55
as an etching stopper, to form an opening portion
64
in the amorphous Si layer
63
.
Referring next to
FIG. 3C
, another amorphous Si layer is formed on the entire surface by deposition, into a thickness of, e.g., 0.12 &mgr;m or less. Anisotropic etching is then carried out to form Si spacers
65
, which newly define an opening portion
66
between them.
Referring next to
FIG. 4A
, anisotropic etching is carried out using the amorphous Si layer
63
and the Si spacers
65
as etching masks, to form a via-hole
67
.
Referring next to
FIG. 4B
, a thick amorphous Si layer
68
doped with, e.g., P (phosphorus), is formed on the entire surface by deposition.
Referring next to
FIG. 4C
, polishing by CMP method is carried out until the surface of the insulating interlayer
55
is exposed. The part of the doped amorphous Si layer
68
formed on the insulating interlayer
55
is thereby removed to form a Si plug
69
filling in the via-hole
67
.
Next, a manufacturing method of a conventional hybrid system LSI including a DRAM will be described with reference to
FIGS. 5A and 5B
to
FIGS. 14A and 14B
, in which a via-hole for a storage node is formed through a PSC process among techniques for forming such a via-hole in a self aligning manner.
FIGS. 5A
,
7
A,
9
A,
11
A and
13
A are sectional views of a memory cell portion.
FIGS. 5B
,
7
B,
9
B,
11
B and
13
B are sectional views of an alignment mark portion at the same stages as those of
FIGS. 5A
,
7
A,
9
A,
11
A and
13
A, respectively.
FIGS. 6A
,
8
A,
10
A,
12
A and
14
A are sectional views perpendicular to those of
FIGS. 5A
,
7
A,
9
A,
11
A and
13
A, respectively.
FIGS. 6B
,
8
B,
10
B,
12
B and
14
B are sectional views of a logic transistor portion.
Referring first to
FIGS. 5A
to
6
B, electrically insulating regions
72
for element isolation are formed in a p-type silicon substrate
71
through an STI (Shallow Trench Isolation) process.
The p-type silicon substrate
71
may be substituted by a p-type well formed in an n- or p-type silicon substrate. Besides, channel stop regions or doped channel regions may be formed therein through an ion implantation process, at need.
Next, a gate oxide film
73
is formed by thermal oxidation using wet O
2
gas. An amorphous Si film is then formed by deposition into a thickness of, e.g., 100 nm. The amorphous Si film is doped with As or P by ion implantation. A conductive Si gate electrode layer
74
is obtained thereby.
Next, a 100 nm-t
Anezaki Toru
Ikemasu Shinichiroh
Fujitsu Limited
Jr. Carl Whitehead
Nguyen Thanh
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