Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2001-03-27
2002-10-08
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S666000, C257S689000, C257S690000, C257S692000, C257S696000, C257S773000
Reexamination Certificate
active
06462408
ABSTRACT:
TECHNICAL FIELD
The present invention relates to aggregating integrated circuits and, in particular, to stacking integrated circuits.
BACKGROUND OF THE INVENTION
A variety of techniques are used to stack integrated circuits. Some require that the circuits be encapsulated in special packages, while others use circuits in conventional packages. In some cases, the leads alone of packaged circuits have been used to create the stack and interconnect its constituent elements. In other techniques, structural elements such as rails are used to create the stack and interconnect the constituent elements.
Circuit boards in vertical orientations have been used to provide interconnection between stack elements. For example, in U.S. Pat. No. Re. 36,916 to Moshayedi, a technique is described for creating a multi-chip module from surface-mount packaged memory chips that purportedly uses sideboards to mount the assembly to the main or motherboard. The devices are interconnected on their lead-emergent sides through printed circuit boards (PCBs) oriented vertically to a carrier or motherboard that is contacted by connective sites along the bottom edge of the PCBs. Other systems purport to use sideboard structures such as Japanese Patent Laid-open Publication No. Hei 6-77644 which discloses vertical PCBs used as side boards to interconnect packaged circuit members of the stack.
Others have stacked integrated circuits without casings or carrier plates. Electrical conductors are provided at the edges of the semiconductor bodies and extended perpendicularly to the planes of the circuit bodies. Such a system is shown in U.S. Pat. No. 3,746,934 to Stein.
Still others have stacked packaged circuits using interconnection packages similar to the packages within which the integrated circuits of the stack are contained to route functionally similar terminal leads in non-corresponding lead positions. An example is found in U.S. Pat. No. 4,398,235 to Lutz et al. Simple piggyback stacking of DIPs has been shown in U.S. Pat. No. 4,521,828 to Fanning.
Some more recent methods have employed rail-like structures used to provide interconnection and structural integrity to the aggregated stack. The rails are either discrete elements that are added to the structure or are crafted from specific orientations of the leads of the constituent circuit packages. For example, in U.S. Pat. No. 5,266,834 to Nishi et al., one depicted embodiment illustrates a stack created by selective orientation of the leads of particularly configured stack elements, while in U.S. Pat. No. 5,343,075 to Nishino, a stack of semiconductor devices is created with contact plates having connective lines on inner surfaces to connect the elements of the stack.
More sophisticated techniques have been recently developed for stacking integrated circuits. The assignee of the present invention has developed a variety of such techniques for stacking integrated circuits. In one such method, multiple conventional ICs are stacked and external leads are interconnected with one another by means of a rail assembly. The rails are made of flat strips of metal and the rails define apertures that receive the leads of the discrete IC packages. An example of this system is shown in U.S. Pat. No. 5,778,522 assigned to the assignee of the present invention.
An even more recent technique developed by the assignee of the present invention interconnects conventionally packaged ICs with flexible circuits disposed between stack elements. The flexible circuits include an array of flexible conductors supported by insulating sheets. Terminal portions of the flexible conductors are bent and positioned to interconnect appropriate leads of respective upper and lower IC packages.
Some of the previously described systems have required encapsulation of the constituent ICs in special packages. Still others have added rails that must be custom-fabricated for the application. Many have relied upon connections that substantially coincide with the vertical orientation of the stack and thus require more materials. Many techniques add excessive height to the stack. Others that use PCBs have inhibited heat dissipation of the stack. Most have deficiencies that add expense or complexity or thermal inefficiency to stacked integrated circuits. What is needed, therefore, is a technique and system for stacking integrated circuits that provides a thermally efficient, robust structure while not adding excessive height to the stack yet allowing production at reasonable cost with easily understood and managed materials and methods.
SUMMARY OF THE INVENTION
The present invention provides a system and method for selectively stacking and interconnecting individual integrated circuit devices to create a high-density integrated circuit module. It is principally designed for use with memory circuits, but can be employed to advantage with any type of packaged and leaded integrated circuit where area conservation and use of duplicative circuitry are present considerations.
In a preferred embodiment, conventional thin small outline packaged (TSOP) memory circuits are vertically stacked one above the other. The stack consists of two packaged integrated circuits (ICs), but alternatives may employ greater numbers of ICs. In a stacked module created in accordance with the present invention, the constituent IC elements act in concert to provide an assembly of memory capacity approximately equal to the sum of the capacities of the ICs that constitute the assembly. The IC elements of the stack are electrically connected through individual contact members that connect corresponding leads of IC elements positioned adjacently in the stack. In a preferred embodiment, the contact members are composed of lead frame material. In a preferred embodiment, two TSOP memory circuits are differentially enabled by extension of a conductive runner from one contact member positioned at the no-connect (N/C) lead of the lower TSOP to another contact member connected to chip-enable lead of the upper TSOP.
Methods for creating stacked integrated circuit modules are provided that provide reasonable cost, mass production techniques to produce modules. In a preferred method, a carrier frame of lead frame material is configured to present an opening into which opening project plural lead-like contact members that correspond to the leads of an IC element. The contact members contact the leads of the lower IC element of the stack while the leads of the upper IC of the assembly contact the upper surfaces of the contact members. The stack is assembled using typical surface mount equipment and, after assembly, the carrier portion of the frame is removed to leave the plurality of contact members in place between selected leads.
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Denko J. Scott
Staktek Group L.P.
Wojciechowicz Edward
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