Contact-less array of fully self-aligned, triple...

Details Contact-less array of fully self-aligned, triple... Contact-less array of fully self-aligned, triple...

1998-05-22

2002-02-12

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S900000

Reexamination Certificate

active

06346725

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention relates to semiconductor non-volatile memory technology and more particularly to a structure of and a method for producing a contact-less array of self-aligned, triple polysilicon, source-side injection, flash memory cells.
2. Description of Related Art
FIGS. 1A-1C
show different perspectives of a contact-less array of triple-polysilicon, source side injection, flash EPROM cells disclosed by Ma et al. in U.S. Pat. No. 5,280,446 issued Jan. 18, 1994, and incorporated herein by reference.
In
FIG. 1A
, each cell includes a drain diffusion
40
, a source diffusion
50
, a floating gate
10
(first layer poly), a control gate
20
(second layer poly), and a select gate
30
(third layer poly). The floating gate
10
and the control gate
20
extend over a first portion L
1
of the channel region L. The source diffusion
50
is laterally spaced a distance L
2
from the floating gate
10
. L
2
forms a second portion of the channel region L. The drain diffusion
40
is self-aligned with the stack of floating gate
10
and control gate
20
. This cell structure is commonly referred to as “split gate” because it merges two serially connected transistors (i.e., the select gate transistor and the floating gate transistor) into a single memory cell. The select gate
30
extends in a direction which is perpendicular to a drain extension, and runs over the drain diffusion
40
, the control gate
20
, the portion L
2
of the channel region L, and the source diffusion
50
of every cell in a row of such cells.
A layout diagram of two rows of memory cells, each row corresponding to the cross section view of
FIG. 1A
, is shown in FIG.
1
B. The floating gates are shown as the cross hatched regions
10
; the drain diffusions are connected together forming a column
40
(drain bitline); the source diffusions are connected together forming another bitline column
50
(source bitline); the control gates are connected together forming yet another column
20
(polysilicon line); and the select gates are connected together forming a row
30
(wordline) perpendicular to the columns.
The drain and source diffusion bitlines are strapped with metal lines (not shown) to minimize the resistance associated with the diffusion bitlines. This is necessary in order to achieve the desired read and programming characteristics. Contacts are used to strap the diffusion bitlines with metal (e.g., one contact may be used every 64 or 128 cells). The number of contacts used along these bitlines depends on the technology and performance requirements. This type of array architecture is commonly referred to as a contact-less array because, unlike the conventional common source array architecture (wherein one contact is required for every two cells), the contact design rules do not limit the size of the cell. Therefore, scaling of the memory cell in such contact-less array architecture is made easier.
FIG. 1C
is a circuit diagram of two rows and six columns of memory cells corresponding to the cross section and layout views in
FIGS. 1A and 1B
, respectively. This diagram shows the mirror image formation of the memory cells along each row, i.e., every two adjacent memory cells along a row are mirror images of one another.
The read, programming and erase operations of this array architecture are described in detail in the above-mentioned '446 patent. Suffice it to state that programming is achieved through source side injection, and erasing is achieved through tunneling between the floating gate and the drain diffusion.
This flash EPROM approach possesses a number of drawbacks. First, during the deposition and definition of select gates
30
(FIGS.
1
A and
1
B), poly stringers form between adjacent rows of select gates
30
, causing electrical shorts between them. The stringers form because the select gates
30
overlay a tall stack of first and second layer poly (approximately 4,000 Å high), and the conventional select gate etch, used in both the periphery and the array regions, does not fully remove the third layer poly in the array region, leaving behind poly stringers. Thus, additional etching in the array region is needed. Since the third layer poly in the periphery region does not require the over etching, an additional masking step is needed.
Second, the second layer poly (control gate
20
) can not receive tungsten silicide (WSi
2
) due to the step height of the poly stack. Incorporating a tungsten silicide layer in the already tall stack of triple poly only exacerbates the problems associated with this stack, such as the stringers. However, without tungsten silicide, the RC time constant associated with control gates
20
is large, causing slow programming and erase functions.
Third, in high density memory devices, due to the typically large RC time delay associated with the polysilicon wordlines (select gates
30
), strapping of the polysilicon wordlines with metal is required in order to achieve reasonable address access time. Such strapping requires drop contacts for making electrical contact between the poly wordline and the metal strap. The drop contacts result in larger array area.
Fourth, during the select gate oxidation step wherein the select gate oxide is formed, a phenomenon, commonly referred to as “cusping”, occurs which results in a number of reliability problems.
FIGS. 2A-2D
illustrate this phenomenon.
FIG. 2A
shows the cross section of a stack of first layer polysilicon
10
(poly
1
) and second layer polysilicon
20
(poly
2
), the tunnel oxide
80
under poly
1
, and the overlying layer of oxide
70
. In
FIG. 2B
, the oxide layer
70
is removed through a dip off process, which as shown, results in removal of portions
81
of the tunnel oxide
80
under the outside edges of poly
1
. In
FIG. 2C
, the gate oxidation step wherein gate oxide
90
is grown over the entire cell, results in raising of the outside edges of both poly
1
and poly
2
. This phenomenon is commonly referred to as “smiling poly”. When the third layer of poly
30
(poly
3
) is deposited over the gate oxide
90
, as shown in
FIG. 2D
, the contours of poly
1
result in “cusping” of poly
3
(i.e., poly
3
is pinched in the areas under the two ends of poly
1
as shown in the encircled region
82
).
Cusping of poly
3
results in a number of reliability problems. First, the raised edges of poly
1
result in thicker tunnel oxide under these edges. This in turn results in slower erase since erase occurs through the tunnel oxide region between poly
1
and the drain diffusion
40
in the area marked as
82
. Second, the oxide under the edges of poly
1
is formed from oxidized poly
1
, which is a poor quality oxide. Such oxide possesses many trap sites which degrade the cycling characteristics of the device. Third, the cusping of poly
3
causes device failures due to charge loss during such reliability procedures as high voltage, high temperature dynamic burn-in cycles. Fourth, the cusping causes early retention failures during retention bake because the sharp corner of the cusp results in high fields.
SUMMARY
In accordance with the present invention, a fully self-aligned, triple polysilicon, source side injection, nonvolatile memory cell suitable for use in a contact-less array of such cells wherein wordlines are overlaid with metal, as well as a method for producing the same is provided.
The following outlines one set of process steps for producing such contact-less array of nonvolatile memory cells in a silicon substrate: (a) a plurality of pairs of stacks of first and second layer polysilicon are formed along a row over the substrate; (b) a drain region is then formed in the substrate between the two stacks in each pair of polysilicon stacks, each drain region being self-aligned to the edges of the two stacks; (c) side-wall spacers are then formed adjacent to edges of each polysilicon stack; and (d) a source region is then formed in the substrate between each of two adjacent pairs of polysilicon stacks, the source region being self-aligne

Affiliated with

Also associated with

Rating

Contact-less array of fully self-aligned, triple... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Contact-less array of fully self-aligned, triple..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Contact-less array of fully self-aligned, triple... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2960358