Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1998-12-03
2001-12-04
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S640000, C438S725000
Reexamination Certificate
active
06326312
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for fabricating a semiconductor device and, more particularly, to a contact hole of a semiconductor device and its forming method constituted by selectively etching an insulating layer to provide the contact hole with double slopes.
2. Discussion of Related Art
As a rule, a process of forming the metal line in a device such as DRAM is constituted by providing a cap structure of the metal line (conductive layer
itride layer) and forming a sidewall by way of deposition/etching step of the nitride layer, with the cap structure and the sidewall being used as an etching-resistant layer in forming a contact hole, which process is termed SAC (Self Aligned Contact).
A conventional method of forming a contact hole of a semiconductor device will be described below in connection with the attached drawings.
FIGS. 1
a
-
1
f
are cross-sectional views illustrating the formation of a contact hole making use of the SAC according to prior art.
As shown in
FIG. 1
a,
a conductive layer
12
for forming a lower line is first formed on a semiconductor substrate
11
, followed by forming a first nitride layer
13
on the conductive layer
12
.
Next, a photo resist overlies the first nitride layer
13
and undergoes exposure and development, patterned into a first mask pattern
14
.
As shown in
FIG. 1
b,
using the first mask pattern
14
as a mask, the first nitride layer
13
and the conductive layer
12
are selectively etched to form a first nitride layer pattern
13
a
and a lower line
12
a.
As shown in
FIG. 1
c,
following removal of the first mask pattern
14
, a second nitride layer
15
is formed on the whole surface of the semiconductor substrate
11
including the first nitride pattern
13
a
and the lower line
12
a.
As shown in
FIG. 1
d,
the second nitride layer
15
is etched back, forming a second nitride layer sidewall
15
a
on both sides of the first nitride layer pattern
13
a
and the lower line
12
a.
As shown in
FIG. 1
e,
a planarizing insulating layer
16
is formed by the SOG (Spin On Glass) on the whole surface of the semiconductor substrate
11
including the lower line
12
a
encompassed with cap layers such as the second nitride side wall
15
a
and the first nitride layer pattern
13
a.
A photo resist overlies the planarizing insulating layer
16
, followed by exposure and development, forming a second mask pattern
17
.
A contact hole
18
is then formed by conducting the SAC, making use of the second mask pattern
17
as a mask, as illustrated in FIG.
1
.
Such as in the prior art above described, the process of forming a contact hole by the SAC of a semiconductor device uses a nitride layer as an etching-resistant layer on the surface of and on the lateral sides of the lower line
12
a.
In order to have a high etching selective ratio, it is preferable to thicken the nitride layer which is used as a cap layer for preventing short-circuits between the lines.
Though not shown in the figures, the subsequent process is constituted by providing a conductive plug inside the contact hole and forming the upper line which is electrically connected to the lower line via the conductive plug.
However, such a conventional process of forming a contact hole of a semiconductor device involves some problems as follows:
First, an increase in the thickness of the nitride layer used as a cap layer for encompassing the conductive material increases the period of time for the process, and the increased thickness of the nitride layer at the edge of the metal line in the SAC process limits the reduction of the design rules.
Secondly, the cap layer is needed to encompass the conductive material, resulting in an increase in the time and costs required for the entire process.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a contact hole of a semiconductor device and its forming method that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a contact hole of a semiconductor device and its forming method which is adapted to reduce the time and costs for the entire process with a consequence of higher reliability of the device.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a contact hole of a semiconductor device includes: an insulating layer formed on a semiconductor substrate; and a contact hole having double slopes, exposing a defined region of the semiconductor substrate.
Further, a method of forming the contact hole of a semiconductor device includes the steps of: forming a conductive layer on a semiconductor substrate, and subsequently a first mask pattern on the conductive layer; selectively eliminating the conductive layer making use of the first mask pattern as a mask, forming a lower line; removing the first mask pattern, and forming an insulating layer on the whole surface of the semiconductor substrate including the lower line; forming a second mask pattern on the insulating layer; etching the insulating layer to a specified depth making use of the second mask pattern as a mask, accumulating a polymer layer on the lateral sides of and on the lower part of the etched insulating layer, thereby forming the upper part of the contact hole having a first slope; and forming the lower part of the contact hole having a second slope, making use of the polymer layer and the second mask pattern as a mask, thereby exposing a defined portion of the surface on the semiconductor substrate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5338399 (1994-08-01), Yanagida
patent: 5378654 (1995-01-01), Hsue
patent: 5550071 (1996-08-01), Ryou
patent: 5562801 (1996-10-01), Nulty
patent: 5783496 (1998-07-01), Flanner et al.
patent: 6028001 (2000-02-01), Shin
patent: 6037261 (2000-03-01), Jost et al.
patent: 6191042 (2001-02-01), Tsai et al.
S. Wolf, et al. “Silicon Processing for the VLSI Era, vol. 1”Lattice Press, pp. 540-541. 1986.
Everhart Caridad
LG Semicon Co. Ltd.
Morgan & Lewis & Bockius, LLP
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