Contact for memory cells

Details Contact for memory cells Contact for memory cells

2002-09-24

2003-08-26

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S145000, C365S164000, C365S072000

Reexamination Certificate

active

06611449

ABSTRACT:

BACKGROUND OF THE INVENTION
FIG. 1
shows a cross-section of a ferroelectric memory cell
101
. The memory cell includes a transistor
130
formed on a substrate
105
. The transistor includes a gate
133
and first and second diffusion regions
131
and
132
. A capacitor
140
is coupled to one of the diffusion regions of the transistor via a conductive lower capacitor plug
151
. The capacitor includes a ferroelectric layer
144
disposed between first and second electrodes
143
and
145
. Typically, a barrier layer
142
is provided between the plug and the electrode of the capacitor to inhibit diffusion of oxygen which can oxidize the plug. An encapsulation layer
167
is provided over the capacitor. The encapsulation layer serves to prevent hydrogen from penetrating the ferroelectric layer.
Coupled to the other diffusion region is a plug. The plug can be coupled to, for example, a bitline. In some applications (e.g., series architecture), the other diffusion region is coupled to the top capacitor electrode
145
. Series architectures, for are described in Takashima et al.,
IEEE JOURNAL. SOLID
-
STATE CIRCUITS
, VOL. 33, pp 787-792, May 1998 and “A Sub−40ns Chain FRAM Architecture with 7ns Cell-Plate-Line Drive”,
IEEE JOURNAL OF SOLID
-
STATE CIRCUITS
. VOL.34. NO. 1, which are herein incorporated by reference for all purposes. Typically, the plug is formed in two processes. The first process forms a lower portion
174
. Above the lower portion of the plug is a barrier layer
176
to protect the gate stack and contact from oxidizing during an oxygen recovery anneal.
During processing, the gate oxide of the transistor suffers degradation due to charging up of the interface states. To repair the gate oxide, a hydrogen containing anneal is performed. The anneal is performed during back-end-of-line (BEOL) process. However, the encapsulation and the lower barrier layers prevent hydrogen from penetrating to the transistor to anneal the damage of the gate oxide.
From the foregoing discussion, it is desirable to provide a diffusion path for hydrogen to improve the properties of the gate oxide.
SUMMARY OF THE INVENTION
The invention relates generally to memory ICs. More particularly, the invention relates to ferroelectric ICs. In one embodiment, a memory cell includes a transistor having a gate and first and second diffusion regions formed on a substrate. A capacitor is coupled to one of the diffusion regions via a first plug. A second plug is coupled to the second diffusion region.
In accordance with one embodiment of the invention, the second plug comprises first and second sections. The second section overlaps the first section to create a gap for diffusion of hydrogen to the transistor to anneal the gate oxide damage.


REFERENCES:
patent: 5789320 (1998-08-01), Andricacos et al.
patent: 5866946 (1999-02-01), Kamigaki et al.
patent: 6037235 (2000-03-01), Narwankar et al.
patent: 6281535 (2001-08-01), Ma et al.
patent: 6320213 (2001-11-01), Kirlin et al.
patent: 6365927 (2002-04-01), Cuchiaro et al.
US patent application Publication US 2002/0040988 by Hidaka et al.

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