Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1999-01-06
2001-03-20
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S700000, C438S736000, C438S637000, C430S312000, C430S313000, C430S317000, C430S394000
Reexamination Certificate
active
06204187
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to an improved method and apparatus for forming contacts.
2. Description of the Related Art
Contact patterning is becoming more and more difficult for lithography with decreasing groundrules. For memory and/or logic chips, such as, dynamic random access memory (DRAM) chips and embedded DRAM chips, sub-micron groundrules may be used, for example. Sub-micron line space patterns can be printed reasonably well with relatively simple image enhancement techniques (e.g., off-axis illumination).
Printing sub-micron contacts is much more difficult, however. Since contact holes are typically formed as individual holes, aberrations and interference patterns occurring during patterning make reliable formation of the contact holes difficult even if advanced techniques such as phase shift masks are used.
The alignment of contacts with conductors, such as metal lines, is important. When contacts and metal lines are smaller in size, alignment becomes even more difficult, and missing a connection between the metal line and the contact as well as shorting out a contact and a neighboring line may be more likely.
Therefore, a need exists for improved contacts for semiconductor devices wherein the contacts may be formed down to the size of the groundrules. A further need exists for a method of forming the improved contacts wherein the risk of misalignment with metal lines is reduced.
SUMMARY OF THE INVENTION
A method for patterning semiconductor components includes the steps of providing a substrate layer, the substrate layer having a dielectric layer formed thereon and a mask layer formed on the dielectric layer, the mask layer being selectively etchable relative to the dielectric layer, patterning the mask layer to form a first group of substantially parallel lines in the mask layer and patterning the dielectric layer to form rectangular holes therein down to the substrate layer.
Another method for patterning semiconductor components, in accordance with the present invention, includes the steps of providing a substrate layer, the substrate layer having a dielectric layer formed thereon, a first mask layer formed on the dielectric layer and a second mask layer formed on the first mask layer, the second mask layer and the dielectric layer being selectively etchable relative to the first mask layer, patterning the second mask layer to form a first group of substantially parallel lines in the second mask layer, patterning the first mask layer to form rectangular holes therein, etching the dielectric layer in accordance with the rectangular holes to form rectangular holes in the dielectric layer and removing remaining portions of the first mask layer and the second mask layer.
Yet another method for patterning semiconductor components includes the steps of providing a substrate layer, the substrate layer having a dielectric layer formed thereon, a first mask layer formed on the dielectric layer, the first mask layer and the dielectric layer being selectively etchable relative to each other, patterning a resist on the first mask layer by forming substantially parallel lines, etching through the first mask layer in accordance with the patterned resist to form a first group of substantially parallel lines in the first mask layer, removing the resist, patterning a second resist on the first mask layer by forming a second group of substantially parallel lines disposed substantially perpendicular to the first group of substantially parallel lines, etching through the dielectric layer in accordance with the patterned second resist and the first group of substantially parallel lines to form rectangular holes in the dielectric layer, removing the second resist and removing remaining portions of the first mask layer.
In other methods in accordance with the present invention, the step of depositing a conductive material in the holes to form contacts to the substrate layer may be included. The substrate layer may include a semiconductor substrate and the method include the step of etching the semiconductor substrate to form deep trenches therein. The method may further include the step of forming the holes into shapes including one of rectangles and squares. The step of forming holes may include the step of forming holes into shapes including one of rectangles and squares wherein at one least side the rectangles and squares includes a minimum feature size of a given technology. The method may further include the steps of independently adjusting a length of the rectangular holes and/or independently adjusting a width of the rectangular holes. The method may further include the steps of etching lines in the dielectric layer corresponding to hole positions and depositing a conductive material in the holes and in the lines for a dual damascene process.
A semiconductor device in accordance with the present invention includes a substrate including contact regions, a dielectric layer disposed on the substrate having rectangular holes disposed therein according to a predetermined pattern and a plurality of rectangular contacts disposed in the rectangular holes for connecting the contact regions of the substrate to a conductive layer disposed on the dielectric layer.
In alternate embodiments, the rectangular contacts have at least one side substantially equal to at least a minimum feature size for a given technology. The rectangular contacts may be squares with sides substantially equal to at least a minimum feature size for the given technology. The contact regions may include diffusion regions and the conductive layer includes bitlines. The dielectric layer may include dual damascene metal lines for electrically connecting to the contacts.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
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Rupp Thomas S.
Thomas Alan
Zach Franz
Infineon Technologies North America Corp.
Paschburg Donald B.
Rocchegiani Renzo N.
Smith Matthew
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