Construction process for a self-aligned transistor

Details Construction process for a self-aligned transistor Construction process for a self-aligned transistor

1990-03-20

1991-08-06

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156646, 156653, 156657, 1566611, 156662, 437 41, 357 239, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

050375059

ABSTRACT:
Disclosed is a device enabling a transistor of submicronic gate length to be constructed using optical means of masking. The process includes a stage during which a resin, deposited on a wafer of semiconducting materials, is etched in order to isolate a pattern as a future gate mask. The mask is eroded, and a layer of silica deposited. Because of the erosion, the sides of the pattern and of the mask are inclined. After etching of the layer of silica and the masking resin, there remain therefore two silica masks whose sloping sides leave a submicronic aperture, through which the gate is deposited.

REFERENCES:
patent: 4472872 (1984-09-01), Toyoda et al.
patent: 4488351 (1984-12-01), Momose
patent: 4577392 (1986-03-01), Peterson
patent: 4784718 (1988-11-01), Mitani et al.
IBM Technical Disclosure Bulletin, vol. 25, No. 3A, Aug. 1982, New York, U.S., L. M. Ephrath et al.: "Self-Aligned Gate Process Using Pattern Transfer for High Speed MESFET Fabrication", pp. 1189-1193.
Journal fo the Electrochemical Society, vol. 133, No. 10, Oct. 1986, pp. 409C-416C, Manchester, NH, U.S.; C. E. Weitzel et al.: "A Review of GaAs MESFET Gate Electrode Fabrication Technologies".

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