Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – With lattice constant mismatch
Reexamination Certificate
2007-04-10
2007-04-10
Baumeister, B. William (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
With lattice constant mismatch
C257SE21125
Reexamination Certificate
active
10915362
ABSTRACT:
A construction of thin strain-relaxed SiGe layers and method for fabricating the same is provided. The construction includes a semiconductor substrate, a SiGe buffer layer formed on the semiconductor substrate, a Si(C) layer formed on the SiGe buffer layer, and an relaxed SiGe epitaxial layer formed on the Si(C) layer. The Si(C) layer is employed to change the strain-relaxed mechanism of the relaxed SiGe epitaxial layer formed on the Si(C) layer. Therefore, a thin relaxed SiGe epitaxial layer with low threading dislocation density, smooth surface is available. The fabricating time for fabricating the strain-relaxed SiGe layers is greatly reduced and the surface roughness is also improved.
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patent: 6291321 (2001-09-01), Fitzgerald
patent: 6660393 (2003-12-01), Saitoh et al.
patent: 2003/0107032 (2003-06-01), Yoshida
Chen Lih-Juann
Chen Pang-Shiu
Lee Sheng-Wei
Liao Kao-Feng
Liu Chee-Wee
Baumeister B. William
Harness & Dickey & Pierce P.L.C.
Industrial Technology Research Institute
Reames Matthew L.
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