Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2000-06-22
2003-01-21
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S118000, C702S119000, C702S120000, C702S183000, C702S185000, C702S189000
Reexamination Certificate
active
06510398
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to integrated circuit devices, and more particularly, to structural testing of integrated circuit devices.
BACKGROUND
Testing of integrated circuit die or a packaged component including circuitry (generally referred to as a device under test (DUT)) at the time they are manufactured and before they are incorporated into a next level assembly is generally necessary to ascertain the functionality of the DUT. A microprocessor, for instance, should be tested before it is incorporated into a next level assembly to avoid the cost of discarding the microprocessor, or to avoid a costly diagnosis and repair after it is assembled into the next level assembly.
Traditionally, microprocessors and integrated circuit devices have been subjected to functional testing using an external tester. These external testers contain a large memory that stores test data patterns of ones and zeros used as inputs to the microprocessor along with patterns of correct outputs expected from the microprocessor. The drawback of functional testing is that the external tester performance has to keep up with microprocessor performance improvements, and the writing of test data patterns for functional testing can take as much as 60 to 100 man-years. Also the functional testing generally increases tester data volume and application time. To circumvent the problem of increased tester data volume and application time, a special test mode is designed into the microprocessor circuitry. When this mode of operation is selected, the internal state of nodes in the microprocessor circuitry can be accessed, initialized and controlled directly from the tester without having to run through the functional inputs and outputs that are used in normal operation mode. This type of test mode to test the microprocessor accomplishes the testing of the structure of the microprocessor and not the whole function of the microprocessor. Testing the microprocessor using the special test mode is generally known as “structural testing”. Structural testing can considerably reduce the test data volume and test application time, and it permits using automatic tools to program the tester, which in turn reduces the time required to write test data patterns.
Further simplification and reduction in testing costs are obtained by using Built-In Self-Test (BIST) methodology. BIST uses random data patterns to test the DUT in the test mode (when using random data patterns in the test mode, the state elements are configured in a long daisy chain, such that the test data moves serially from one state element to another, and eventually the test data comes out of an external pin in the DUT). The term “state elements” in this document refers to essentially a part of the microprocessor circuit that potentially holds data for at least one clock cycle. The use of these random data patterns considerably reduces the volume of stored bits on a tester, thereby significantly simplifying and reducing the cost of testing the DUTs.
BIST also uses signature analyzers to compress the test results into a single, smaller pattern or “signature” to reduce the amount of tester memory and circuitry required. The signature is then analyzed to determine whether the DUT is free of structural defects. For BIST, the random pattern generator and the signature analyzer circuitry are both built right into the DUT itself. This eliminates the need for using an external tester to test the DUT.
However, the random data patterns applied (applying data patterns means applying 0's and 1's to energize various parts of circuitry in the DUT) to test the DUT should not damage the device due to a burnout. Devices are generally designed to operate in response to functional patterns, and the application of random data patterns can set up electrically undesirable configurations. For example it is possible that multiple drivers on the same circuit node are turned on, creating an electrical short circuit from the power supply to ground (when applying random data patterns during a test mode, it is possible that some state elements in the scan chain are joined together creating an electrical short circuit from the power supply to ground). This configuration, also referred to as “bus contention”, can potentially result in burnout or reliability issues in the DUT (this joining of state elements to cause an electrical short circuit is referred to as “bus contention” problems). Such configurations are generally ruled out by design in the functional mode, but it is extremely difficult and expensive to guarantee that they will not arise during the application of random data patterns.
Another problem generally associated with BIST is that some of the state elements in the scan chain could be in a critical path, and they can cause a significant delay in a signal propagating through these state elements (serially coming in and out of these state elements in the scan chain) during the test mode, and this may not be acceptable. To circumvent this problem, these state elements may not be scanned (configured to be part of a serial shift register in test mode). Not scanning a state element results in a loss of control over the value at its output node (nodes are generally a specific kind of state element) during a test, when random data patterns are being shifted into the scanned elements. This can result in a non-deterministic (unpredictable) value at the output node of the non-scan state element. The resulting non-deterministic value at the output node is generally referred to as “X-generation”. For example, in an adder, let us assume that we are adding two 32-bit entities which produces one 33-bit quantity. During this process, if we exclude scanning one of the inputs to the adder (say we exclude one 32-bit quantity), because this bit is in the critical path, and can cause significant delay during testing, this can result in some of the bits in the final test result to be unknown values. Suppose we are adding 3+2=5 in the adder;in a binary representation is 11, and 2 in a binary representation is 10. If one of them is in the critical path, and if we decide not to scan one of the two-bit entities when we are adding these two-bit entities, we may get an X
0
as the output instead of 10. This unknown value generated during adding is referred to as the “X-generation.” One way to circumvent this problem is to do the functional testing on these unscanned state elements that are in the critical path. Doing functional testing on some state elements generally requires modifying a design of the DUT circuitry, and it can result in significant delay and undue penalty in terms of final performance of the integrated circuit devices (adding this additional circuitry to test the DUT is generally referred to as “design for testability overhead”, also referred to as “DFT overhead”). Generally, for a structural testing to succeed, all of the internal state/storage elements must be considered in the scan chain. Leaving some elements out in the test mode can result in lack of controllability and observability.
Therefore there is a need for a structural test that can circumvent bus contention problems and X-generation problems during testing of a DUT, and that yet can provide the advantages of random pattern testing such as collateral test coverage, reduced DFT overhead, controllability and observability of the DUTs during testing.
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Galivanche Rajesh
Kundu Sandip
Sengupta Sanjay
Hoff Marc S.
Tsai Carol S
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