Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
1998-02-23
2002-10-08
Ho, Tuan (Department: 2612)
Television
Camera, system and detail
Solid-state image sensor
C348S315000
Reexamination Certificate
active
06462779
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor based image sensors, and more specifically, to linear sensors having variable resolution modes.
BACKGROUND OF THE INVENTION
The ability to offer a “fast preview” mode on scanning image systems is a feature many customers find desirable, as it offers a quick means for viewing the document or object to be scanned, and enables the document or object to be adjusted for an optimal scan much faster than can be achieved using “regular” scanning speeds and resolutions. In conventional CCD structures, it is possible to sum adjacent charge packets (i.e., pixels) on or before the charge detection node (e.g., floating diffusion) to obtain a spatial resolution of half the non summed image. However, this charge summing technique requires that the CCD clocks be operated at two times the full resolution rate to maintain the original pixel readout rate. In many high speed applications, such as the scanning of motion picture film in real-time, the CCD structures are operated at very high frequencies, often the maximum possible operating frequency the imager can support. Therefore, double the CCD clock rates is not an option. Another situation which sets a limit on the maximum pixel data rate is the analog-to-digital converter (ADC). High resolution scanners often use state-of-the-art ADCs in the 14 to 16 bit range. These converters typically have maximum conversion rates much lower than the maximum possible CCD clocking frequency, and hence limit the maximum pixel data rate. As in the case above, doubling the CCD clock frequency and summing adjacent pixels on the change detection node is necessary to obtain a ½ resolution image. Designing a CCD driver to support the ½ resolution, 2× CCD speed mode of operation yields a more expensive circuit and hence is very undesirable.
The two-phase CCD structure presented herein requires no additional CCD phases and only one additional pin. If the half resolution feature is not necessary in a given application, the CCD clocks are operated using conventional waveforms, so this feature would not cause existing systems to become more complicated.
SUMMARY OF THE INVENTION
The invention described herein is a charge coupled device (CCD) structure which permits both full and half spatial resolution images to be readout while maintaining a constant pixel readout rate and constant CCD clocking rates. In conventional CCD structures, it is possible to sum adjacent charge packets (i.e., pixels) on the charge detection node (e.g., floating diffusion) to obtain a spatial resolution of half the non summed image. However, this charge summing technique requires that the CCD clocks be operated at two times the full resolution rate to maintain the original pixel readout rate. In many high speed applications, such as the scanning of motion picture film in real-time, the CCD structures are operated at very high frequencies, often the maximum possible operating frequency. Therefore, double the CCD clock rates is not an option. The CCD structure presented requires no additional CCD phases and only one additional pin. If the half resolution feature is not necessary in a given application, the CCD clocks are operated using conventional waveforms, so this feature would not cause existing systems to become more complicated.
This invention can be used on both linear and area CCD based image sensors. It does require one additional clock signal (pin) per CCD. When operating the CCD in the half resolution mode, some of the CCD clocks need to be operated at above normal voltage levels.
ADVANTAGES OF THE INVENTION
The novel CCD architecture described herein offers several advantages over conventional CCD structures, as summarized below:
1. Allows half resolution images to be output using constant speed CCD clocks and ~½ the total line period.
2. Allows scanning applications to perform half resolution scans at approximately half the full resolution rate.
3. Requires only one additional input clock (pin).
4. If not used, the CCD structure is operated using conventional input clocks, so no changes required.
5. When implemented in a color multi-channel linear imager, this CCD structure enables programmable color resolution.
6. Can be used on both one and two dimensional CCD image sensors.
REFERENCES:
patent: 4317134 (1982-02-01), Woo et al.
patent: 4554585 (1985-11-01), Carlson
patent: 5326997 (1994-07-01), Nakanishi
patent: 5486711 (1996-01-01), Ishida
patent: 5502578 (1996-03-01), Smitt
patent: 5691937 (1997-11-01), Ohta
patent: 5777672 (1998-07-01), Cazaux et al.
Eastman Kodak Company
Ho Tuan
Watkins Peyton C.
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