Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
2000-08-28
2003-02-11
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S775000, C257S691000, C257S690000, C257S693000, C257S692000, C257S698000, C257S662000, C257S786000, C361S704000, C361S748000, C174S255000, C174S250000
Reexamination Certificate
active
06518663
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related in general to the field of semiconductor devices and processes and more specifically to structure and materials of high-performance plastic ball-grid array packages designed for integrated circuit assembly.
DESCRIPTION OF THE RELATED ART
Ball Grid Array (BGA) packages have emerged as an excellent packaging solution for integrated circuit (IC) chips with high input/output (I/O) count. BGA packages use sturdy solder balls for surface mount connection to the “outside world” (typically plastic circuit boards, PCB) rather sensitive package leads, as in Quad Flat Packs (QFP), Small Outline Packages (SOP), or Tape Carrier Packages (TCP). Some BGA advantages include ease of assembly, use of surface mount process, low failure rate in PCB attach, economic use of board area, and robustness under environmental stress. The latter used to be true only for ceramic BGA packages, but has been validated in the last few years even for plastic BGAs. From the standpoint of high quality and reliability in PCB attach, BGA packages lend themselves much more readily to a six-sigma failure rate fabrication strategy than conventional devices with leads to be soldered.
A BGA package generally includes an IC chip, a multi-layer substrate, and a heat spreader. The chip is generally mounted on the heat spreader using a thermally conductive adhesive, such as an epoxy. The heat spreader provides a low resistance thermal path to dissipate thermal energy, and is thus essential for improved thermal performance during device operation, necessary for consistently good electrical performance. Further, the heat spreader provides structural and mechanical support by acting as a stiffener, adding rigidity to the BGA package, and may thus be referred to as a heat spreader/stiffener.
One of the substrate layers includes a signal “plane” that provides various signal lines, which can be coupled, on one end, to a corresponding chip bond pad using a wire bond (or to a contact pad using flip-chip solder connection). On the other end, the signal lines are coupled with solder “balls” to other circuitry, generally through a PCB. These solder balls form the array referred to in a BGA. Additionally, a ground plane will generally be included on one of the substrate layers to serve as an active ground plane to improve overall device performance by lowering the inductance, providing controlled impedance, and reducing cross talk. These features become the more important the higher the BGA pin count is.
In contrast to the advantages of the BGA packages, prevailing solutions in BGA packages have lagged in performance characteristics such as power dissipation and the ability to maintain signal integrity in high speed operation necessary for devices such as high speed digital signal processors (DSP) and mixed signal products (MSP). Electrical performance requirements are driving the need to use multi-layer copper-laminated resin substrates (previously ceramic). As clock frequencies and current levels increase in semiconductor devices, the packaging designs are challenged to provide acceptable signal transmission and stable power and ground supplies. Providing stable power is usually achieved by using multiple planes in the package, properly coupled to one another and to the signal traces. In many devices, independent power sources are needed for core operation and for output buffer supply but with a common ground source.
As for higher speeds, flip chip assembly rather than wire bonding has been introduced. Compared to wire bonding within the same package outline, flip chip assembly offers greatly reduced IR drop to the silicon core circuits; significant reduction of power and ground inductances; moderate improvement of signal inductance; moderate difference in peak noise; and moderate reduction in pulse width degradation.
In order to satisfy all these electrical and thermal performance requirements, packages having up to eight metal layers have been introduced. The need, however, of high numbers of layers is contrary to the strong market emphasis on total semiconductor device package cost reduction. This emphasis is driving an ongoing search for simplifications in structure and materials, of course with the constraint that electrical, thermal and mechanical performances should be affected only minimally
In U.S. patent application Ser. No. 60/147,596, filed Aug. 6, 1999, to which this invention is related, the structure and fabrication method of a high-performance, high I/O plastic BGA has been discussed. There are only two metal layers, one of which is exclusively devoted to a ground plane. The package has thus a small thickness and a low cost. But the remaining metal layer has a crowded routing density, since all signal and power lines of the high I/O device have to share this one layer. Consequently, the Vcc inductances are too high for fast-speed processor devices. The high inductance is the source of unacceptable electrical noise and cross talk, severely limiting device speed.
The signal lines in today's semiconductor package substrates suffer in their electrical performance (for instance, signal integrity and cross talk) because their characteristic impedance is not constant due to the fact that the lines have to be routed with non-uniform spacings to neighboring lines in the crowded line layout.
An urgent need has therefore arisen to break this vicious cycle and conceive a concept for a low-cost, yet high performance electrical connection on dielectric substrates, especially in BGA package structures. Preferably, this structure should be based on a fundamental design concept flexible enough to be applied for different semiconductor product families and a wide spectrum of design and assembly variations. It should not only meet high electrical and thermal performance requirements, but should also achieve improvements towards the goals of enhanced process yields and device reliability. Preferably, these innovations should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.
SUMMARY OF THE INVENTION
According to the present invention, an electrical connection web is provided, operable at high frequency and configured on a dielectric substrate, comprising a plurality of generally parallel signal lines having graduated width and variable spacings, and said widths and spacings cooperatively selected such that the characteristic impedance of said signal lines is approximately the same for each line of said plurality and approximately constant over the length of each said signal line, whereby signal integrity for each said line is enhanced and cross talk between said lines is reduced.
According to electromagnetic theory, the impedance Z of an ac current of circular frequency &ohgr; is expressed by the relation
Z=
(
R
2
+X
2
)
E
½
.
In this equation, the resistance R relates to the Ohmic resistance as modified by the high-frequency skin effect, and the reactance X relates to the inductance &ohgr;L and the capacitance 1/&ohgr;C as follows:
X=&ohgr;L
−1/&ohgr;C.
With increasing frequency &ohgr;, the contribution to the reactance X and the impedance Z by the inductance L is increasing, while the contribution by the capacitance C is decreasing.
The phase difference between current and voltage is usually denoted as &psgr;. The following relations hold:
sin &psgr;=−
X/Z;
cos &psgr;=
R/Z;
tg&psgr;=−X/R.
For two impedances Z
1
(having resistance R
1
, reactance X
1
, and phase difference &psgr;
1
) and Z
2
(having resistance R
2
, reactance X
2
, and phase difference &psgr;
2
) in series, the total impedance Ztotal is
Z
total=[
Z
1
2
+Z
2
2
+
2
Z
1
Z
2
cos(&psgr;
1
−&psgr;
2
)]
E
½
.
For two impedances Z
1
and Z
2
in parallel, the total impedance Ztotal is
1
/Z
total=[1
/Z
1
2
+1
/Z
2
2
+2/(
Z
1
Z
2
)cos(&psgr;
1
−&psgr;
2
)]
E
½
.
For designing signal lines in an IC package
James Richard D.
Lamson Michael A.
Brady III Wade James
Skrehot Michael K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Williams Alexander O.
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