Electronic digital logic circuitry – Tri-state – With field-effect transistor
Reexamination Certificate
2000-02-14
2002-02-19
Tokar, Michael J. (Department: 2819)
Electronic digital logic circuitry
Tri-state
With field-effect transistor
C326S027000
Reexamination Certificate
active
06348814
ABSTRACT:
FIELD OF THE INVENTION
The field of the present invention relates to buffer circuits and methods, and particularly to buffer circuits providing substantially constant output signal edges.
BACKGROUND OF THE INVENTION
Output buffer circuits with highly controlled output edge rates are well known. Such circuits are however typically produced subject to substantial process variations which cause concomitant undesired performance variations. Some such buffer circuits manufactured will thus be fabricated to have fast processes which cause long signal ringing until stabilization occurs. Other such buffers are fabricated to have slow processes which take inordinately long to reach a desired signal level. Particular buffer circuits with fast processes operating at low temperatures and at high VDD voltages are known to produce a high edge rate which is suitable for strong output driver applications. However, such fast processes produce undesirable voltage reflections from bus line loads, such as receiver integrated circuits (ICs). Bus timing must then be adjusted to enable damping of reflections to a voltage level permitting effective operation. With slow processes operating at a high temperature and at a low VDD voltage, a slow edge rate is produced having a diminished drive capacity of the bus, which possibly causes the far end of the signal bus not to switch in time. Bus timing must thus be adjusted to allow for a weak output driver. Data transfer, particularly on large, heavily loaded buses, is thus limited by the range of edge rates at the output of CMOS buffers for both fast and slow processes. In general, CMOS output buffer circuits do have an advantage in that they dissipate substantially no static, i.e., direct current(DC) power, unless terminating resistors are added to the buses.
Various design approaches have been developed to reduce the edge rate range of CMOS output buffers. For example, a pair of predrive transistors with gates that drive output pullup and pulldown transistors have been constructed which are longer than the minimum length required to limit process variation in the predriver edge rate. According to another example, predriver transistors have been activated with complex predriver gates, e.g., as with another known output buffer circuit which reduces variability of the edge rate as a function of the number of control signals used and the complexity of the control circuitry itself. A substantial area of silicon is however consumed by such complex predriver gate circuitry. According to another approach, extra loading is applied at the outputs of the predriver transistors to adjust the predriver edge rate. This correspondingly adjusts the edge rate of the output transistors. This approach however relies upon use of multiple control signals for fine edge rate selection. The loads for such predriver circuitry however also consume a considerable silicon area.
It is accordingly desirable to develop simple buffer circuits which consume only limited space on an integrated circuit semiconductor substrate and which produce output signals of enhanced timing flexibility based on edge rate control.
SUMMARY OF THE INVENTION
A buffer circuit according to the present invention provides substantially constant output signal edges, thereby serving as an enhanced bus driver with enhanced output stability independent of process and operating conditions. The buffer circuit includes a NOR gate and a NAND gate for driving output pulldown and pullup transistors with enhanced current devices connected to the gates of the pullup and pulldown transistors. The initiation and maintenance of current flows through the NOR and NAND gates of the buffer circuit according to the present invention is controlled by a reference circuit. First and second transistors are provided respectively between the NAND gate and the pullup transistor, and between the NOR gate and the pulldown transistor to produce enhanced sourcing and sinking currents. According to the method of the present invention, sinking and sourcing currents to the pulldown and pullup are terminated by switching of the pulldown and pullup transistors and feedback to the transistors producing the enhanced sourcing and sinking currents. Analog, self-setting circuitry, according to the present invention, sets the control lines from first and second analog voltage reference generators having a direct current (DC) input to control the buffer circuit output edge rate and for a limited time, to control the turn-on voltage of the output pullup and pulldown transistors. The output edge rate variation from the buffer circuit according to the present invention is accordingly substantially reduced. Changes in voltage and temperature are further automatically compensated by the analog reference circuit controlling the buffer circuit, according to the present invention.
REFERENCES:
patent: 5066872 (1991-11-01), Schenck
patent: 5081374 (1992-01-01), Davis
patent: 363294123 (1988-11-01), None
patent: 403227113 (1991-10-01), None
Cadenca Design Systems, Inc.
Chang Daniel D.
Schipper John
Tokar Michael J.
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