Constant CMOS driver

Details Constant CMOS driver Constant CMOS driver

1999-12-30

2002-06-04

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S086000, C327S108000

Reexamination Certificate

active

06400176

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
Embodiments of the present invention relate to driver circuits for driving transmission lines, and more particularly to complementary metal oxide semiconductor (CMOS) driver circuits.
2. Background
A dominant limitation of conventional manufactured driver circuits is their artificially low transmission rates due to widely varying operating conditions, such as voltage, temperature, and process variation. Due to varied operating conditions, the propagation delay and the output impedance of drivers varies widely, thus, hampering impedance matching.
Propagation delay can vary typically by a factor of two to three across two extreme operating conditions. This variation of propagation delay seriously impacts system timing at higher frequencies. Without a constant delay across all operating conditions, system timing is adversely impaired such that timing margins have to be introduced to handle any delay time variations due to varying operating conditions.
A most common and useful communication topology is peer-to-peer connections with full duplex transmission. To achieve optimal impedance matching in this type of topology, the output impedance of the transmitting side must match the characteristic impedance of the transmission line. Impedance matching at the transmitting end has traditionally been accomplished by placing a series resistor between the output driver and the transmission line. For this method to work, the output impedance of the output driver must be kept much lower than the characteristic impedance of the transmission line. This results in a much higher cost in area and power than required for merely transmitting a signal. Moreover, impedance matching is degraded due to varying resistance across operating conditions and the non-linearity of the driver. Another method is to use the nonlinear transistors of the output driver to approximate the linear characteristic impedance of the transmission line. This attempt, however, results in even worse impedance matching than a series resistor placed at the transmitting end.
FIG. 1
illustrates an I/O (input/output) driver
102
communicating with a receiver
104
via a transmission line
106
. The transmission line
106
has a characteristic impedance Z
o
, and may be the physical layer of a bus. The driver
102
and the receiver
104
are complementary metal oxide semiconductor (CMOS) circuits. For purposes of mathematical analysis, the input impedance (Z
in
) of the receiver
104
is approximated as being infinite relative to other impedances in the circuit. The receiver
104
may be one or more CMOS logic gates, or a differential amplifier.
The driver
102
is transmitting an electromagnetic wave travelling in the transmit direction
108
. If Z
in
, of the receiver
104
is not equal to Z
o
, then a reflected wave will propagate in the receiver direction
110
. If the impedance of the driver
102
is not matched to the characteristic impedance Z
o
, then another reflected wave will again be generated, but now travelling in the transmit direction
108
. There will be many multiple reflections, and the electric and magnetic field vectors at any point along the transmission line
106
is the vector sum (superposition) of the transmitted field vector and all reflected field vectors at that point. This superposition of the transmitted wave and the reflected waves may cause signal degradation, which typically limits, for longer transmission lines, the speed at which digital data is reliably transmitted from the driver
102
to the receiver
104
.
The first reflected wave can be reduced by terminating the receiving end of the transmission line
106
with a receiver or stub having an impedance matched to Z
o
. This may, however, require the use of an off-chip resistor, and furthermore, power may be wasted due to ohmic losses in the resistor. Another negative impact of impedance matching at the receiver end is loss of amplitude, potentially halving the amplitude, which can then make the transmitting signal susceptible to noise.
SUMMARY
According to one aspect of the invention, a circuit is provided that includes a drive stage having an input and output node, and at least one transistor coupled between the two nodes. An upper impedance element coupled at one end to the output node and at another end to an upper supply node is provided. The upper impedance element has a stack of transistors each having a beta matched to a beta of at least one transistor in the drive stage. A lower impedance element coupled at one end to the output node and at another end to a lower supply node is provided. The lower impedance element has a stack of transistors each having a beta matched to the beta of at least one transistor in the drive stage.
In another embodiment, a circuit is provided that includes a plurality of transistors coupled in parallel between a supply node and a pre-drive stage. The plurality of transistors each have a gate coupled to a delay select line to control current through the pre-drive stage (a stage before the output driver, i.e., coupled to the input node of the driver).


REFERENCES:
patent: 5361003 (1994-11-01), Roberts
patent: 5732027 (1998-03-01), Arcoleo et al.
patent: 5959473 (1999-09-01), Sakuragi
patent: 6097223 (2000-08-01), Loughmiller
patent: 6137317 (2000-10-01), Griffin

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