Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-10-24
2006-10-24
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C710S019000
Reexamination Certificate
active
07127572
ABSTRACT:
Systems and methods for reducing the number of unit attentions provided to a set of initiator devices by eliminating unnecessary unit attentions from queues in which unit attentions for each of the initiator devices are stored. In one embodiment, a system comprises a processor and a memory implemented in a router that is coupled between a target device and multiple initiator devices. As each unit attention is generated by the target device, it is forwarded to the initiator device that prompted the unit attention, and is stored in a queue for each of the other initiator devices. Periodically, the queues are examined to determine whether any of the unit attentions stored therein are unnecessary. One or more of the unit attentions that are determined to be unnecessary may be eliminated from the respective queues, reducing the number of unit attentions that are provided to the respective initiator devices.
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Gao LinLin
Tyndall John F.
Whittington Robert D.
Crossroads Systems Inc.
Nguyen Hiep T.
Sprinkle IP Law Group
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