Consolidation of allocated memory to reduce power consumption

Details Consolidation of allocated memory to reduce power consumption Consolidation of allocated memory to reduce power consumption

2001-07-30

2004-05-25

Verbrugge, Kevin (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S158000

Reexamination Certificate

active

06742097

ABSTRACT:

TECHNICAL FIELD
This invention relates to power conservation in memory devices and systems.
BACKGROUND
Dynamically refreshed memory, usually referred to as dynamic random access memory or DRAM, is a type of memory device found in many different computing devices. A typical DRAM device may have millions, billions or even more DRAM memory cells. A DRAM memory cell is commonly formed by a single transistor and an associated capacitance. The capacitance is charged to a voltage that indicates a bit value of either “0” or “1”. The capacitance loses its charge rather quickly, bringing about the need for periodic refreshing.
In many computer systems, the power consumption of DRAM memory is insignificant compared to other system components such as hard disks, high-performance microprocessors, active matrix displays, CRTs, etc. However, in other computer systems, such as the newly emerging and evolving class of mobile devices known as “handhelds” or “PDAs” (“personal digital assistants”), the power consumption of the DRAM memory is significant as compared to other components in the computer system. In comparison to many of the more traditional types of computers, such as desktop or personal computers, many mobile computing devices, are smaller, less capable, and use components that consume less power. For example, many of these systems have small, monochromic displays, low performance CPUs, and no hard disks. Some of these mobile systems, furthermore, rely on batteries for their operating power. As a result of these factors, power consumption of memory subsystems has become more of an issue in these devices; there is a strong need to reduce memory power consumption and to thereby extend the time between required battery replacement or recharging.
Memory devices with power management features are becoming available to address this need. For example, DRAMs are available that support various different reduced power modes. However, power savings come at the cost of performance. Typically, a greater penalty in access speed is imposed at each increasing degree of power savings. Thus, decisions regarding whether to invoke power-saving features in a DRAM should be made intelligently. Typically, it is desired to initiate a low power mode in a particular memory device only when that memory device is not currently in use and is not anticipated to be in use in the near future.
It is difficult, however, to anticipate the future need for accessing any particular region of memory. Furthermore, modem operating systems typically allocate memory without regard to memory device boundaries, making it difficult to find a single memory device that can appropriately be set to a reduced power mode without significantly impacting overall system performance. More specifically, typical memory allocation schemes often result in a highly fragmented memory space, with allocated pages of memory spread more or less randomly across the available range of physical memory. Because allocated memory is normally spread across all of the available devices, none of the devices can be put into a reduced power mode without seriously impacting memory performance.
An article entitled “Power Aware Page Allocation,” by authors Alvin R. Lebeck, Xiaobo Fan, Heng Zeng, and Carla Ellis, in Proceedings of the Ninth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-IX) (November, 2000), discusses the desirability of clustering memory page allocations into the minimum number of memory devices. Such clustering allows other devices to be put into reduced power modes.
Described below are specific techniques for minimizing the number of actual DRAM devices being used in a system at any particular time. Such techniques can be implemented in existing systems with very little overhead, while potentially achieving significant power savings.


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