Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-11-06
2003-05-13
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S675000, C438S700000
Reexamination Certificate
active
06562714
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of fabricating deep trench DRAM devices in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, deep trench (DT)-based dynamic random access memory (DRAM) devices require certain integration practices. It has been customary to separate the contact etches in the array area from the contact etches in the periphery. Different fill materials (polysilicon in the array area and tungsten in the periphery, for example) and different contact methods (diffusion contact in the array area and implant contact in the periphery) are reasons for the separation. However, in DRAM devices with a design rule of less than 150 nm, a low resistivity material is required for an array contact, especially for those using a deep trench as a storage node. Thus, polysilicon is no longer an attractive option for the contact in the array area because of its high resistivity, especially in the ease of deep trench based DRAM design.
It has also been customary to combine the bit substrate contact (CS) etch with the contact to gate etch because of their close proximity in the array area. For example, a self-aligned contact (SAC) process has been used for the bit line contact (CB) etch in the array area while the contact to substrate and the gate contact etch in the periphery have been etched together with a moderate oxide-to-nitride etch selectivity (<3:1) etch method. The moderate etch selectivity recipe has been chosen partly because it must etch through a nitride capping layer on top of the gate. However, this moderate etching selectivity, especially of oxide to nitride, puts the future manufacturing process in jeopardy due to insufficient overlay control between the gate contact and the contact to the substrate in the periphery. Overlay control becomes more difficult as the ground rule (or critical dimension of the gate) shrinks especially for those devices having a ground rule of less than 0.17 &mgr;m. The protection for gate conductor (GC) against CS short becomes even weaker with insufficient selectivity. A proximity of the CS to the gate is a dangerous event. Deleterious short channel effect, threshold voltage roll-off (lowering of the threshold voltage as gate length decreases), junction leakage, and lowering of the effective saturation current can result. This is especially true for implanted contact devices such as NFET support devices.
A number of patents have addressed aspects etching selectivity. U.S. Pat. No. 5,718,800 to Juengling teaches selective contact etching using a nitride cap layer. U.S. Pat. No. 5,292,677 to Dennison discloses a single etch stop layer for all contacts wherein all contacts are opened together. U.S. Pat. No. 6,136,643 to Jeng et al, U.S. Pat. No. 6,133,153 to Marquez et al, and U.S. Pat. No. 5,965,035 to Hung et al show contact etches that are selective to oxide with respect to nitride. U.S. Pat. No. 6,008,104 to Schrems shows a DRAM process with several selective etches.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide an effective and very manufacturable method of DRAM formation in the fabrication of integrated circuits.
It is a further object of the invention to provide a consolidated junction contact etch for DRAM device fabrication.
In accordance with the objects of the invention, a consolidated junction contact etch in the fabrication of a DRAM integrated circuit device is achieved. Semiconductor device structures are provided in and on a substrate wherein the substrate is divided into an array area and a periphery area. The semiconductor device structures are covered with an etch stop layer. A dielectric layer is deposited over the etch stop layer. The dielectric layer is concurrently etched through in the array area to form bit line contact openings, in the periphery area to form substrate contact openings, and to form gate contact openings wherein the etching stops at the etch stop layer. The etch stop layer is etched into to a lesser extent through the substrate contact openings and the bit line contact openings than through the gate contact openings. Then, the etch stop layer is etched through using a directional etch selective to the substrate layer (silicon). The bit line contact openings, substrate contact openings, and gate contact openings are cleaned by a wet process and filled with a conducting layer to complete formation of contacts in the fabrication of a DRAM integrated circuit device.
REFERENCES:
patent: 5292677 (1994-03-01), Dennison
patent: 5965035 (1999-10-01), Hung et al.
patent: 6326270 (2001-12-01), Lee et al.
Ackerman Stephen B.
Le Dung A
Nelms David
Pike Rosemary L. S.
ProMos Technologies Inc.
LandOfFree
Consolidation method of junction contact etch for below 150... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Consolidation method of junction contact etch for below 150..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Consolidation method of junction contact etch for below 150... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3023140