Console chip and single memory bus system

Details Console chip and single memory bus system Console chip and single memory bus system

2006-08-15

2006-08-15

Perveen, Rehana (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S306000, C710S240000, C710S107000

Reexamination Certificate

active

07093053

ABSTRACT:
A single memory bus multi-media computer system is provided, including a CPU/Sound/Graphic unit, a bus arbitrator, a program and sound and graphic memory for communicating with the CPU/Sound/Graphic unit and the bus arbitrator. Only a single memory bus is required as communication is through the bus arbitrator. The addition of the bus-arbitrator can relieve the CPU/Sound/Graphic unit from performing bus synchronization and waiting for the slow memory to catch up.

REFERENCES:
patent: 5566306 (1996-10-01), Ishida
patent: 5630174 (1997-05-01), Stone et al.
patent: 5802597 (1998-09-01), Nelsen
patent: 6012089 (2000-01-01), Hasegawa
patent: 6205524 (2001-03-01), Ng
patent: 2003/0204853 (2003-10-01), Fries et al.

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