Consistent packet switched memory bus for shared memory multipro

Details Consistent packet switched memory bus for shared memory multipro Consistent packet switched memory bus for shared memory multipro

1994-01-27

1999-07-13

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711119, G06F 1200

Patent

active

059241195

ABSTRACT:
A shared memory multiprocessor having a packet switched bus for transferring data between a plurality processors, I/O devices, cache memories and main memory employs a bus protocol which permits multiple copies of data to be updated under the control of different processors while still ensuring that all processors and all I/O devices have access to consistent values for all data at all times.

REFERENCES:
patent: 4426681 (1984-01-01), Bacot et al.
patent: 4442487 (1984-04-01), Fletcher et al.
patent: 4451880 (1984-05-01), Johnson et al.
patent: 4535448 (1985-08-01), Baxter et al.
patent: 4622631 (1986-11-01), Frank et al.
patent: 4843542 (1989-06-01), Dashiell et al.
David V. James edited by Dubois et al., "Cache and Interconnect Architectures in Multiprocessors, SCI (Scalable Coherent Interface) Cache Coherence, " Academic Publishers, 1990, pp. 189-208.
Andrew W. Wilson, Jr., "Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors," Computer Architecture Conference (IEEE/ACM), 1987, pp. 244-252.

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